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User’s Manual U19678EJ1V1UD
911
CHAPTER 19 RESET FUNCTION
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) or input voltage (EXLVI) from
external input pin, and detection voltage
(5) Internal reset by execution of illegal instruction
Note 1
(6) Internal reset by a reset processing check error
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal
is generated.
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
circuit voltage detection or execution of illegal instruction
Note 1, and each item of hardware is set to the status shown in
Tables 19-1 and 19-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization
time just after a reset release, except for P140
Note 2, which is low-level output.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high
level is input to the RESET pin and program execution is started with the internal high-speed oscillation clock after
reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the
internal high-speed oscillation clock (see Figures 19-2 to 19-4) after reset processing. Reset by POC and LVI circuit
power supply detection is automatically released when VDD
≥ VPOR or VDD ≥ VLVI after the reset, and program
execution starts using the internal high-speed oscillation clock (see CHAPTER 20 POWER-ON-CLEAR CIRCUIT
and CHAPTER 21 LOW-VOLTAGE DETECTOR) after reset processing.
Notes 1.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
2.
48-pin products of 78K0R/IC3, 78K0R/ID3 and 78K0R/IE3 only.
Cautions 1. For an external reset, input a low level for 10
μs or more to the RESET pin.
(To perform an external reset upon power application, a low level of at least 10
μs must be
continued during the period in which the supply voltage is within the operating range (VDD
≥
2.7 V).)
2. During reset input, the X1 clock, XT1 clock (in the products other than the 78K0R/IB3), internal
high-speed oscillation clock, and internal low-speed oscillation clock stop oscillating.
External main system clock input becomes invalid.
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held
during reset input.
4. When reset is effected, port pin P140 is set to low-level output and other port pins become
high-impedance, because each SFR and 2nd SFR are initialized.
Remark
VPOR: POC power supply rise detection voltage