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參數(shù)資料
| 型號(hào)： | UPD78F1235GK-GAJ-AX |
| 廠商： | Renesas Electronics America |
| 文件頁(yè)數(shù)： | 453/1067頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | MCU 16BIT 78K0R/LX3 64-LQFP |
| 標(biāo)準(zhǔn)包裝： | 300 |
| 系列： | 78K0R/Ix3 |
| 核心處理器： | 78K/0R |
| 芯體尺寸： | 16-位 |
| 速度： | 40MHz |
| 連通性： | 3 線 SIO，I²C，LIN，UART/USART |
| 外圍設(shè)備： | DMA，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 50 |
| 程序存儲(chǔ)器容量： | 64KB（64K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 3K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 64-LQFP |
| 包裝： | 托盤 |
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
443
7.5.9 Operation as A/D conversion trigger output function (type 2)
The A/D conversion trigger output function uses two channels in combination to output A/D conversion triggers.
It outputs A/D conversion trigger signals from slave channels.
Multiple slave channels can be used to increase the number of A/D conversion trigger outputs.
The A/D conversion trigger output function assumes the slave channel to be used as a sub-function of the function
described in 7.5.6 Operation as 6-phase triangular wave PWM output function. The setting of the master channel
is therefore the same as in 7.5.6 Operation as 6-phase triangular wave PWM output function.
The A/D
conversion trigger pulse generation period can be calculated by the following expression.
A/D conversion trigger pulse generation period (interval from the start of the carrier period to INTTMn
detection during a down status) = {Set value of TDRm (slave) + 1}
× Count clock period
Setting range of TDRm (slave): 0000H
< TDRm (slave) < {Set value of TDRn (master) + 1}
* Interval from INTTMm detection during a down status to INTTMm detection during an up status
= {{Set value of TDRn (master) + 1}
{Set value of TDRm (slave)}} × 2 × Count clock period
TCRn of the master channel operates in the interval timer mode and counts the periods.
TCRn loads the value of TDRn by setting the channel start trigger bit (TSn) to 1.
Afterward, TCRn counts down along with the count clock. When TCRn has become 0000H, INTTMn is output and
TOn is toggled upon the next count clock. TCRn loads the value of TDRn again at the same timing. Similar operation
is continued hereafter.
A carrier period is generated in two periods of the master channel count.
The count operation of the slave channel is controlled by defining the first period of the master channel as a down
status of the slave channel and the second period as an up status of the slave channel.
TOn of the master channel outputs up and down statuses.
TOn of the TO0 register must be manipulated while TOEn of the TOE0 register is 0 and the default level must be
set, because up and down statuses are output.
TOn of the TO0 register is set to 1 when MDn0 of the TMR0 register is 0, and TOn is set to 0 when MDn0 is 1.
By setting the default level, a high level is output from TOn during a down status and a low level is output during an
up status.
TCRm of slave channel m operates in the up and down count mode, and counts the duty. TRm loads the value of
TDRm at the first count clock, after the channel start trigger bit (TSm) is set to 1. Hereafter, counting up and counting
down is switched in accordance with the operation of the master channel. INTTMm is output when TCRm becomes
0001H.
TCRm loads the value of TDRm again when INTTMn is generated in an up status of the master channel. Similar
operation is continued hereafter.
Remarks 1.
OPM = 0: n = 00, m = 08, 09
OPM = 1: n = 00, 04, m = 01, 05
2.
OPM: Bit 15 of TAU option mode register (OPMR)
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