
CHAPTER 7 INVERTER CONTROL FUNCTIONS
User’s Manual U19678EJ1V1UD
404
Figure 7-27. Operation Procedure When 6-Phase PWM Output Function Is Used (1/2)
Software Operation
Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN and TAUOPEN bits of the PER2
register to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAUS
default
setting
Sets the TPS0 register.
Determines clock frequencies of CK00 and CK01.
Sets the TMR00 and TMRm registers of each channel to
be used (determines operation mode of channels).
An interval (period) value is set to the TDR00 register of
the master channel, and a duty factor is set to the
TDRm register of slave channels 2 to 7.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets slave channels 2 to 7.
Sets the TOMm bit to 1 (slave channel output mode).
Sets the TOTm bit to 0 (generates other than
triangular wave PWM output).
Sets the TOLm bit and determines the active level of
the TOm output.
Sets the TOm bit and determines default level of the
TOm output.
The TOm pin goes into Hi-Z output state.
The TOm default setting level is output when the port mode
register is in output mode and the port register is 0.
Channel
default
setting
Sets the TOEm bit to 1 and enables operation of
TOm.
Clears the port register and port mode register to 0.
TOm does not change because channel has stopped
operating.
The TOm pin outputs the TOm set level.
Operation
start
Sets TOEm (slaves 2 to 7) to 1 (only when operation is
resumed).
The TS00 (master) and TSm (slaves 2 to 7) bits of the
TS0 register are set to 1 at the same time.
The TS00 and TSm bits automatically return to 0
because they are trigger bits.
TE00 = 1, TEm = 1
When the master channel starts counting, INTTM00 is
generated. Triggered by this interrupt, the slave channels
2 to 7 also start counting.
During
operation
Set values of the TDR00 and TDRm registers can be
changed after INTTM00 of the master channel is
generated.
The TCR00 and TCRm registers can always be read.
Set values of the TOL0, TO0, and TOE0 registers can
be changed.
The counter of the master channel loads the TDR00 value to
TCR00 and counts down. When the count value reaches
TCR00 = 0000H, INTTM00 is generated. At the same time,
the value of the TDR00 register is loaded to TCR00, and the
counter starts counting down again.
At slave channels 2 to 7, the values of the TDRm register
are transferred to TCRm, triggered by INTTM00 of the
master channel, and the counter starts counting down. The
output levels of TOm become active one count clock after
generation of the INTTM00 output from the master channel.
It becomes inactive when TCRm = 0000H, and the counting
operation is stopped. After that, the above operation is
repeated.
Remark
m = 02 to 07
Operation
is
re
su
med.
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next
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