
CHAPTER 14 SERIAL INTERFACE IICA
User’s Manual U19678EJ1V1UD
770
Figure 14-6. Format of IICA Control Register 0 (IICCTL0) (3/4)
STT
Note
Start condition trigger
0
Do not generate a start condition.
1
When bus is released (in standby state, when IICBSY = 0):
If this bit is set (1), a start condition is generated (startup as the master).
When a third party is communicating:
When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
When communication reservation function is disabled (IICRSV = 1)
Even if this bit is set (1), the STT bit is cleared and the STT clear flag (STCF) is set (1). No start
condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
For master reception:
Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE
has been cleared to 0 and slave has been notified of final reception.
For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
during the wait period that follows output of the ninth clock.
Cannot be set to 1 at the same time as SPT.
Setting STT to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (STT = 0)
Condition for setting (STT = 1)
Cleared by setting STT to 1 while communication
reservation is prohibited.
Cleared by loss in arbitration
Cleared after start condition is generated by master
device
Cleared by LREL = 1 (exit from communications)
When IICE = 0 (operation stop)
Reset
Set by instruction
Note
The signal of this bit is invalid while IICE0 is 0.
Remarks 1. Bit 1 (STT) becomes 0 when it is read after data setting.
2. IICRSV: Bit 0 of IIC flag register (IICF)
STCF:
Bit 7 of IIC flag register (IICF)