參數(shù)資料
型號(hào)： UPD754304GS-XXX-A
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO36
封裝： 0.300 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁(yè)數(shù)： 37/73頁(yè)
文件大?。?/td> 814K
代理商： UPD754304GS-XXX-A
PD754302, 754304, 754302(A), 754304(A)
42
Data Sheet U10797EJ2V1DS
Instruction
Number
Addressing
Mnemonic
Operand
of machine
Operation
Skip condition
group
of bytes
cycles
area
Comparison
SKE
reg, #n4
2
2+S
Skip if reg = n4
reg=n4
@HL, #n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2+S
Skip if A = reg
A=reg
XA, rp'
2
2+S
Skip if XA = rp'
XA=rp'
Carry flag
SET1
CY
1
CY
← 1
manipulation
CLR1
CY
1
CY
← 0
SKT
CY
1
1+S
Skip if CY = 1
CY=1
NOT1
CY
1
CY
← CY
Memory bit
SET1
mem.bit
2
(mem.bit)
← 1*3
manipulation
fmem.bit
2
(fmem.bit)
← 1*4
pmem.@L
2
(pmem7–2+L3–2.bit(L1–0))
← 1*5
@H+mem.bit
2
(H+mem3–0.bit)
← 1*1
CLR1
mem.bit
2
(mem.bit)
← 0*3
fmem.bit
2
(fmem.bit)
← 0*4
pmem.@L
2
(pmem7–2+L3–2.bit(L1–0))
← 0*5
@H+mem.bit
2
(H+mem3–0.bit)
← 0*1
SKT
mem.bit
2
2+S
Skip if (mem.bit)=1
*3
(mem.bit)=1
fmem.bit
2
2+S
Skip if (fmem.bit)=1
*4
(fmem.bit)=1
pmem.@L
2
2+S
Skip if (pmem7–2+L3–2.bit(L1–0))=1
*5
(pmem.@L)=1
@H+mem.bit
2
2+S
Skip if (H+mem3–0.bit)=1
*1
(@H+mem.bit)=1
SKF
mem.bit
2
2+S
Skip if (mem.bit)=0
*3
(mem.bit)=0
fmem.bit
2
2+S
Skip if (fmem.bit)=0
*4
(fmem.bit)=0
pmem.@L
2
2+S
Skip if (pmem7–2+L3–2.bit(L1–0))=0
*5
(pmem.@L)=0
@H+mem.bit
2
2+S
Skip if (H+mem3–0.bit)=0
*1
(@H+mem.bit)=0
SKTCLR
fmem.bit
2
2+S
Skip if (fmem.bit)=1 and clear
*4
(fmem.bit)=1
pmem.@L
2
2+S
Skip if (pmem7–2+L3–2.bit(L1–0))=1 and clear
*5
(pmem.@L)=1
@H+mem.bit
2
2+S
Skip if (H+mem3–0.bit)=1 and clear
*1
(@H+mem.bit)=1
AND1
CY, fmem.bit
2
CY
← CY ∧ (fmem.bit)
*4
CY, pmem.@L
2
CY
← CY ∧ (pmem7–2+L3–2.bit(L1–0))
*5
CY, @H+mem.bit
2
CY
← CY ∧ (H+mem3–0.bit)
*1
OR1
CY, fmem.bit
2
CY
← CY ∨ (fmem.bit)
*4
CY, pmem.@L
2
CY
← CY ∨ (pmem7–2+L3–2.bit(L1–0))
*5
CY, @H+mem.bit
2
CY
← CY ∨ (H+mem3–0.bit)
*1
XOR1
CY, fmem.bit
2
CY
← CY v (fmem.bit)
*4
CY, pmem.@L
2
CY
← CY v (pmem7–2+L3–2.bit(L1–0))
*5
CY, @H+mem.bit
2
CY
← CY v (H+mem3–0.bit)
*1
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