參數(shù)資料
型號: UPD754304GS-XXX-A
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, MICROCONTROLLER, PDSO36
封裝: 0.300 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁數(shù): 27/73頁
文件大?。?/td> 814K
代理商: UPD754304GS-XXX-A
PD754302, 754304, 754302(A), 754304(A)
33
Data Sheet U10797EJ2V1DS
9. RESET FUNCTION
There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/
watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure
9-1 shows the circuit diagram of the above two inputs.
Figure 9-1. Configuration of Reset Function
Generation of the RESET signal initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing
chart of the reset operation.
Figure 9-2. Reset Operation by RESET Signal Generation
Note
The following two times can be selected by the mask option.
217/fX (21.8 ms : @ 6.0 MHz, 31.3 ms: @ 4.19 MHz)
215/fX (5.46 ms : @ 6.0 MHz, 7.81 ms: @ 4.19 MHz)
RESET
Internal RESET signal
RESET signal sent from the
basic interval timer/watchdog timer
WDTM
Internal bus
Operation mode or
standby mode
Wait Note
RESET
signal
generated
Operation mode
HALT mode
Internal reset operation
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