參數(shù)資料
型號(hào): UPD754304GS-XXX-A
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, MICROCONTROLLER, PDSO36
封裝: 0.300 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁(yè)數(shù): 51/73頁(yè)
文件大?。?/td> 814K
代理商: UPD754304GS-XXX-A
PD754302, 754304, 754302(A), 754304(A)
55
Data Sheet U10797EJ2V1DS
AC Characteristics (TA = –40 to +85
°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle time Note1
tCY
When system
VDD = 2.7 to 5.5 V
0.67
64
s
(Minimum instruction execution
clock is used
time = 1 machine cycle)
0.95
64
s
TI0, TI1 input frequency
fTI
VDD = 2.7 to 5.5 V
0
1
MHz
0
275
kHz
TI0, TI1 input high- and
tTIH, tTIL
VDD = 2.7 to 5.5 V
0.48
s
low-level width
1.8
s
Interrupt input high- and
tINTH, tINTL
INT0
IM02 = 0
Note 2
s
low-level width
IM02 = 1
10
s
INT1, 2, 4
10
s
KR0-7
10
s
RESET low-level width
tRSL
10
s
Notes 1.
The CPU clock (
Φ) cycle time (minimum
instruction execution time) is determined
by the ocillation frequency of the con-
nected resonator and the processor
clock control register (PCC). The figure
on the right shows the cycle time tCY
characteristics against the supply voltage
VDD when the system clock is used.
2.
2tCY or 128/fx depending on the setting of
the interrupt mode register (IM0).
0.5
01
2
3456
1
2
3
4
5
6
60
64
Supply voltage VDD [V]
(During system clock operation)
tCY vs VDD
Operation
guaranteed range
Cycle
time
t
CY
[
s]
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