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參數(shù)資料
| 型號(hào)： | UPD754304GS-XXX-A |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDSO36 |
| 封裝： | 0.300 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36 |
| 文件頁數(shù)： | 26/73頁 |
| 文件大?。?/td> | 814K |
| 代理商： | UPD754304GS-XXX-A |
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PD754302, 754304, 754302(A), 754304(A)
32
Data Sheet U10797EJ2V1DS
8. STANDBY FUNCTION
In order to save dissipation power while a program is in a standby mode, two types of standby modes (STOP
mode and HALT mode) are provided for the
PD754304.
Table 8-1. Operation Status in Standby Mode
Item
Mode
STOP mode
HALT mode
Set instruction
STOP instruction
HALT instruction
Operation
Clock generator
The system clock stops oscillation.
Only the CPU clock
Φ halts (oscillation
status
continues).
Basic interval timer/
Operation stops.
Operable (The IRQBT is set in the
Watchdog timer
reference interval).
Serial interface
Operable only when an external SCK
Operable
input is selected as the serial clock.
Timer/event counter
Operable only when a signal input to
Operable
the TI0 and TI1 pins are specified as
the count clock.
External interrupt
The INT1, 2, and 4 are operable.
Only the INT0 is not operated Note.
CPU
The operation stops.
Release signal
Interrupt request signal sent from the operable hardware enabled by the
interrupt enable flag or RESET signal input.
Note
Operable only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register
(IM0).
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