
89
μ
PD75236
(c)
Shift register 0 (SIO0)
Fig. 4-42 shows a shift register 0 peripheral configuration. SIO0 is an 8-bit register which executes
parallel-to-serial conversion and carries out serial transmission/reception (shift operation) in synchro-
nization with a serial clock.
Serial transfer is started by writing data to SIO0.
In transmission, the data written to SIO0 is output to the serial output (SO0) or serial data bus
(SB0/SB1).
In reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.
This register can be read/written by an 8-bit manipulation instruction.
RESET input during operation makes the SIO0 value undefined. RESET input in the standby mode
holds the SIO0 value.
Shift operation stops after 8-bit transmission /reception.
Fig. 4-42 Shift Register 0 peripheral Configuration
SIO0 read and serial transfer start (write) are enabled at the following timings.
Serial interface operation enable/disable bit (CSIE0) = 1 except when CSIE0 is set to “1”
after data write to the shift register.
When the serial clock is masked after 8-bit serial transfer.
When SCK0 is at a high level
Be sure to write/read data to SIO0 when SCK0 is at a high level.
In the 2-wire serial I/O or SBI mode, the data bus has a configuration that the input pins
serve as output pins and vice versa. Each output pin has an N-ch open drain configuration.
Thus, set FFH to SIO0 for the device for data reception.
Internal Bus
Address
Comparator
Shift
Register 0
Shift Clock
N-ch Open Drain Output
SO0 Latch
CLR
RELT
CMDT
SET
Q
D
CLK
BUSY/ACK
CSIM0