
159
μ
PD75236
Mnemonic
Operands
Machine
Cycle
Skip
Condition
Addressing
Area
Operation
No. of
Bytes
N
B
Note
Instruction Group
SET1
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
BRCB
BR
M
#
mem.bit
2
2
(mem.bit)
←
1
*3
fmem.bit
2
2
(fmem.bit)
←
1
*4
pmem.@L
2
2
(pmem
7-2
+L
3-2
.bit(L
1-0
))
←
1
*5
@H + mem.bit
2
2
(H+mem
3-0
.bit)
←
1
*1
mem.bit
2
2
(mem.bit)
←
0
*3
fmem.bit
2
2
(fmem.bit)
←
0
*4
pmem.@L
2
2
(pmem
7-2
+L
3-2
.bit(L
1-0
))
←
0
*5
@H+mem.bit
2
2
(H+mem
3-0
.bit)
←
0
*1
mem.bit
2
2 + S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2 + S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2 + S
Skip if (pmem
7-2
+L
3-2
.bit(L
1-0
)) = 1
*5
(pmem.@L) = 1
@H+mem.bit
mem.bit
2
2
2 + S
2 + S
Skip if (H+mem
3-0
.bit) = 1
Skip if (mem.bit) = 0
*1
*3
(@H+mem.bit) = 1
(mem.bit) = 0
fmem.bit
2
2 + S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2 + S
Skip if (pmem
7-2
+L
3-2
.bit(L
1-0
)) = 0
*5
(pmem.@L) = 0
@H+mem.bit
2
2 + S
Skip if (H+mem
3-0
.bit) = 0
*1
(@H+mem.bit) = 0
fmem.bit
2
2 + S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2 + S
Skip if (pmem
7-2
+L
3-2
.bit(L
1-0
))=1 and clear
*5
(pmem.@L) = 1
@H+mem.bit
2
2 + S
Skip if (H+mem
3-0
.bit)=1 and clear
*1
(@H+mem.bit)=1
CY, fmem.bit
2
2
CY
←
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
←
CY
(pmem
7-2
+L
3-2
.bit(L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
←
CY
(H+mem
3-0
.bit)
*1
CY, fmem.bit
2
2
CY
←
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
←
CY
(pmem
7-2
+L
3-2
.bit(L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
←
CY
(H+mem
3-0
.bit)
*1
CY, fmem.bit
2
2
CY
←
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
←
CY
(pmem
7-2
+L
3-2
.bit(L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
←
CY
(H+mem
3-0
.bit)
*1
PC
13-0
←
addr
(Optimum instruction is
selected from among BR!
addr, BRCB!caddr and
BR$addr1 by an assembler.)
addr
—
—
*6
$addr
1
2
PC
13-0
←
addr
*7
!addr
3
3
PC
13-0
←
!addr
*6
PCDE
2
3
PC
13-0
←
PC
13-8
+DE
PCXA
2
3
PC
13-0
←
PC
13-8
+XA
BCDE
2
3
PC
13-0
←
BCDE
BCXA
2
3
PC
13-0
←
BCXA
!caddr
2
2
PC
13-0
←
PC
13,12
+caddr
11-0
*8