
106
μ
PD75236
(6)
Transfer start in each mode
In each of the 3-wire and 2-wire serial I/O modes and the SBI mode, serial transfer is started by setting
transfer data to the shift register 0 (SIO0) under the following two conditions.
Serial interface operation enable/disable bit (CSIE0) = 1
The internal serial clock has stopped or SCK0 is at high level after 8-bit serial transfer.
Note
Transfer does not start if CSIE0 is set to “1” after data is written to the shift register 0.
Serial transfer automatically stops and the interrupt request flag (IRQCSI0) is set upon termination of 8-
bit transfer.
[2-wire serial I/O mode transfer start precautions]
Note
Because it is necessary to turn off the N-ch transistor upon data reception, write FFH to SIO0 in
advance.
[SBI mode transfer start precautions]
Note
1. Because it is necessary to turn off the N-ch transistor upon data reception, write FFH to SIO0 in
advance.
However, in the case of wake-up function specify bit (WUP) = 1, the N-ch transistor remains OFF.
Thus, it is not necessary to write FFH to SIO0 before reception.
2. If data is written to SIO0 when the slave is busy, the written data is not lost.
Transfer starts when the busy status is cancelled and the SB0 (or SB1) input becomes high level
(ready status).
Example
The RAM data specified by the HL register is transferred to SIO0 and simultaneously the SIO0 data
is fetched into the accumulator and serial transfer is started.
MOV
SEL
XCH
XA, @HL
MB15
XA, SIO0
; Transmit data is fetched from the RAM.
; or CLR1 MBE
; Transmit data is exchanged with receive data and transfer is started.