
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
Preliminary User’s Manual U17790EJ1V0UD
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(2/2)
Cautions 2. Be sure to follow the steps below when changing the DTFRn register settings.
When the values to be set to bits IFCn5 to IFCn0 are not set to bits IFCm5 to IFCm0 of
another channel (n = 0 to 3, m = 0 to 3, n
≠ m)
<1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0).
<2> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the
settings in the 8-bit manipulation.)
<3> Confirm that DFn bit = 0.
(Stop the interrupt generation source operation
beforehand.)
<4> Enable the DMAn operation (Enn bit = 1).
When the values to be set to bits IFCn5 to IFCn0 are set to bits IFCm5 to IFCm0 of
another channel (n = 0 to 3, m = 0 to 3, n
≠ m)
<1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0).
<2> Stop the DMAm operation of the channel where the same values are set to bits
IFCm5 to IFCm0 as the values to be used to rewrite bits IFCn5 to IFCn0
(DCHCm.Emm bit = 0).
<3> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the
settings in the 8-bit manipulation.)
<4> Confirm that bits DFn and DFm = 0. (Stop the interrupt generation source operation
beforehand.)
<5> Enable the DMAn operation (bits Enn and Emm = 1).
3. An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP, or sub-
IDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1).
4. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an
interrupt occurs from the selected on-chip peripheral I/O, regardless of whether the DMA
transfer is enabled or disabled.
If DMA is enabled in this status, DMA transfer is
immediately started.
Remark
For the IFCn5 to IFCn0 bits, see Table 20-1 DMA Start Factors.