
Preliminary User’s Manual U17790EJ1V0UD
11
4.3.9
Port 9....................................................................................................................................... 131
4.3.10
Port CD.................................................................................................................................... 139
4.3.11
Port CM ................................................................................................................................... 140
4.3.12
Port CS.................................................................................................................................... 142
4.3.13
Port CT .................................................................................................................................... 144
4.3.14
Port DH.................................................................................................................................... 146
4.3.15
Port DL .................................................................................................................................... 148
4.4
Block Diagrams .....................................................................................................................151
4.5
Port Register Settings When Alternate Function Is Used.................................................188
4.6
Cautions .................................................................................................................................198
4.6.1
Cautions on setting port pins ................................................................................................... 198
4.6.2
Cautions on bit manipulation instruction for port n register (Pn) .............................................. 201
4.6.3
Cautions on on-chip debug pins .............................................................................................. 202
4.6.4
Cautions on P05/INTP2/DRST pin .......................................................................................... 202
4.6.5
Cautions on P53 pin when power is turned on ........................................................................ 202
4.6.6
Hysteresis characteristics ........................................................................................................ 202
CHAPTER 5 BUS CONTROL FUNCTION...........................................................................................203
5.1
Features..................................................................................................................................203
5.2
Bus Control Pins ...................................................................................................................204
5.2.1
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed............... 204
5.2.2
Pin status in each operation mode .......................................................................................... 204
5.3
Memory Block Function........................................................................................................205
5.4
External Bus Interface Mode Control Function..................................................................206
5.5
Bus Access ............................................................................................................................207
5.5.1
Number of clocks for access.................................................................................................... 207
5.5.2
Bus size setting function .......................................................................................................... 207
5.5.3
Access by bus size .................................................................................................................. 208
5.6
Wait Function.........................................................................................................................215
5.6.1
Programmable wait function .................................................................................................... 215
5.6.2
External wait function .............................................................................................................. 216
5.6.3
Relationship between programmable wait and external wait ................................................... 217
5.6.4
Programmable address wait function ...................................................................................... 218
5.7
Idle State Insertion Function ................................................................................................219
5.8
Bus Hold Function ................................................................................................................220
5.8.1
Functional outline .................................................................................................................... 220
5.8.2
Bus hold procedure ................................................................................................................. 221
5.8.3
Operation in power save mode................................................................................................ 221
5.9
Bus Priority ............................................................................................................................222
5.10
Bus Timing .............................................................................................................................223
CHAPTER 6 CLOCK GENERATION FUNCTION ...............................................................................229
6.1
Overview.................................................................................................................................229
6.2
Configuration .........................................................................................................................230
6.3
Registers ................................................................................................................................232
6.4
Operation................................................................................................................................237
6.4.1
Operation of each clock ........................................................................................................... 237
6.4.2
Clock output function ............................................................................................................... 237
6.5
PLL Function..........................................................................................................................238