
APPENDIX E REVISION HISTORY
User’s Manual U12768EJ4V1UD
490
(5/7)
Edition
Major Revision from Previous Edition
Applied to:
Figure 12-3 Correspondence Between DRAn Setup Value and Internal RAM Area
Addition
Figure 12-5 DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2) Deletion and
addition of products in Note 2
CHAPTER 12
DMA FUNCTIONS
14.2.1 (4) Block diagram (port 0) Addition
14.2.2 (3) Block diagrams (port 1) Addition
14.2.3 (3) Block diagrams (port 2) Addition
14.2.4 (3) Block diagrams (port 3) Addition
14.2.5 (1) Functions of P4 and P5 pins Modification of description
14.2.5 (3) Block diagram (port 4, port 5) Addition
14.2.6 (3) Block diagram (port 6) Addition
14.2.7 (2) Block diagram (port 7, port 8) Addition
14.2.8 (1) Function of P9 pins Modification of description
14.2.8 (3) Block diagrams (port 9) Addition
14.2.9 (3) Block diagram (port 10) Addition
14.2.10 (3) Block diagrams (port 11) Addition
14.2.11 (1) Function of P12 pin Deletion of description
14.2.11 (3) Block diagram (port 12) Addition
14.3 Setting When Port Pin Is Used for Alternate Function Addition
CHAPTER 14
PORT FUNCTION
16.1.1 Erase units Addition
16.4 (3) CSI0 + HS Addition
Table 16-1 Signal Generation of Dedicated Flash Programmer (PG-FP3) Addition of
CSI0 + HS
Table 16-2 Pins Used by Each Serial Interface Addition of CSI0 + HS
3rd
edition
Table 16-3 List of Communication Systems Addition of CSI0 + HS
CHAPTER 16
FLASH MEMORY
(
PD70F3017A,
70F3017AY)
Addition of
PD703014B, 703014BY, 703015B, 703015BY, 70F3015B, and 70F3015BY
Deletion of
PD703014AGC, 703014AYGC, 703015AGC, and 703015AYGC
Throughout
Addition of Table 1-1 List of V850/SA1 Products
Addition of description to the minimum instruction execution time in 1.2 Features
Deletion and addition of products in 1.4 Ordering Information
Deletion and addition of products in 1.5 Pin Configuration
Deletion of description in 1.6.2 (2) Bus control unit (BCU)
INTRODUCTION
Addition of Table 2-1 Pin I/O Buffer Power Supplies
Modification of description in Table 2-2 Operating States of Pins in Each Operating Mode
Modification of description in 2.3 (7) P60 to P65 (Port 6)
Addition of 2.3 (13) CLKOUT (Clock Out)
Addition and modification of description in 2.4 Pin I/O Circuits and Recommended
Connection of Unused Pins
4th
edition
Modification of 2.5 Pin I/O Circuits
CHAPTER 2 PIN
FUNCTIONS