參數(shù)資料
型號(hào): UPD45128163G5-A10LT-9JF
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)
中文描述: 8M X 16 SYNCHRONOUS DRAM, 6 ns, PDSO54
封裝: PLASTIC, TSOP2-54
文件頁數(shù): 10/86頁
文件大小: 774K
代理商: UPD45128163G5-A10LT-9JF
Data Sheet E0348N10 (Ver. 1.0)
10
μ
PD45128163-T
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst
write operation. The first write data in burst mode can input with this
command with subsequent data on following clocks.
Fig.4 Column address and write command
CLK
/WE
/CAS
/RAS
/CS
CKE
H
Add
A10
BA0(A13), BA1(A12)
Col.
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been
met. This command sets the burst start address given by the column
address.
Fig.5 Column address and read command
CLK
/WE
/CAS
/RAS
/CS
CKE
H
Add
A10
BA0(A13), BA1(A12)
Col.
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh
operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and
ready for a row activate command.
During t
RC
period (from refresh command to refresh or activate
command), the
μ
PD45128xxx cannot accept any other command.
Fig.6 CBR (auto) refresh command
CLK
Add
A10
BA0(A13), BA1(A12)
/WE
/CAS
/RAS
/CS
CKE
H
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