
User’s Manual U14272EJ3V0UM
24
LIST OF FIGURES (1/3)
Fig. No.
Title
Page
1-1.
1-2.
1-3.
1-4.
1-5.
1-6.
1-7.
1-8.
1-9.
Internal Block Diagram ................................................................................................................................ 30
V
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4110 CPU Core Internal Block Diagram ................................................................................................. 35
CPU Registers ............................................................................................................................................ 37
CPU Instruction Formats (32-Bit Length Instruction) .................................................................................. 38
CPU Instruction Formats (16-Bit Length Instruction) .................................................................................. 39
Byte Address in Little-Endian Byte Order .................................................................................................... 41
Unaligned Word Accessing (Little Endian) .................................................................................................. 42
External Circuits of Clock Oscillator ............................................................................................................ 48
Incorrect Connection Circuits of Resonator ................................................................................................ 49
3-1.
3-2.
3-3.
3-4.
3-5.
3-6.
3-7.
3-8.
3-9.
3-10.
3-11.
3-12.
3-13.
3-14.
3-15.
3-16.
3-17.
3-18.
3-19.
3-20.
3-21.
3-22.
3-23.
3-24.
3-25.
3-26.
3-27.
3-28.
Index Register ............................................................................................................................................. 69
Random Register ........................................................................................................................................ 69
EntryLo0 and EntryLo1 Registers ............................................................................................................... 70
Context Register ......................................................................................................................................... 71
PageMask Register ..................................................................................................................................... 72
Positions Indicated by the Wired Register .................................................................................................. 73
Wired Register ............................................................................................................................................ 73
BadVAddr Register ..................................................................................................................................... 74
Count Register ............................................................................................................................................ 74
EntryHi Register .......................................................................................................................................... 75
Compare Register ....................................................................................................................................... 76
Status Register ............................................................................................................................................ 76
Status Register Diagnostic Status Field ...................................................................................................... 77
Cause Register ........................................................................................................................................... 79
EPC Register (When MIPS16 ISA Is Disabled) .......................................................................................... 81
EPC Register (When MIPS16 ISA Is Enabled) ........................................................................................... 82
PRId Register .............................................................................................................................................. 82
Config Register ........................................................................................................................................... 83
LLAddr Register .......................................................................................................................................... 84
WatchLo Register ........................................................................................................................................ 85
WatchHi Register ........................................................................................................................................ 85
XContext Register ....................................................................................................................................... 86
Parity Error Register .................................................................................................................................... 87
Cache Error Register .................................................................................................................................. 87
TagLo Register ............................................................................................................................................ 88
TagHi Register ............................................................................................................................................ 88
ErrorEPC Register (When MIPS16 ISA Is Disabled) .................................................................................. 90
ErrorEPC Register (When MIPS16 ISA Is Enabled) ................................................................................... 90
4-1.
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4181 Physical Address Space ................................................................................................................ 92