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User’s Manual U14272EJ3V0UM
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2.2.7 LED interface signals ...................................................................................................................
2.2.8 CompactFlash interface and keyboard interface signals .............................................................
2.2.9 Serial interface channel 1 signals ................................................................................................
2.2.10 IrDA interface signals ................................................................................................................
2.2.11 General-purpose I/O signals ......................................................................................................
2.2.12 Dedicated V
DD
/GND signals ......................................................................................................
2.3 Pin Status in Specific Status .................................................................................................. 60
2.4 Recommended Connection of Unused Pins and I/O Circuit Types .................................... 63
2.5 Pin I/O Circuits ......................................................................................................................... 66
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CHAPTER 3 CP0 REGISTERS ............................................................................................................ 67
3.1 Coprocessor 0 (CP0) ............................................................................................................... 67
3.2 Details of CP0 Registers ......................................................................................................... 69
3.2.1 Index register (0) .........................................................................................................................
3.2.2 Random register (1) .....................................................................................................................
3.2.3 EntryLo0 (2) and EntryLo1 (3) registers ......................................................................................
3.2.4 Context register (4) ......................................................................................................................
3.2.5 PageMask register (5) .................................................................................................................
3.2.6 Wired register (6) .........................................................................................................................
3.2.7 BadVAddr register (8) ..................................................................................................................
3.2.8 Count register (9) .........................................................................................................................
3.2.9 EntryHi register (10) ....................................................................................................................
3.2.10 Compare register (11) ...............................................................................................................
3.2.11 Status register (12) ....................................................................................................................
3.2.12 Cause register (13) ....................................................................................................................
3.2.13 Exception Program Counter (EPC) register (14) .......................................................................
3.2.14 Processor Revision Identifier (PRId) register (15) .....................................................................
3.2.15 Config register (16) ....................................................................................................................
3.2.16 Load Linked Address (LLAddr) register (17) .............................................................................
3.2.17 WatchLo (18) and WatchHi (19) registers .................................................................................
3.2.18 XContext register (20) ...............................................................................................................
3.2.19 Parity Error register (26) ............................................................................................................
3.2.20 Cache Error register (27) ...........................................................................................................
3.2.21 TagLo (28) and TagHi (29) registers .........................................................................................
3.2.22 ErrorEPC register (30) ...............................................................................................................
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CHAPTER 4 MEMORY MANAGEMENT SYSTEM ............................................................................ 91
4.1 Overview ................................................................................................................................... 91
4.2 Physical Address Space ......................................................................................................... 92
4.2.1 ROM space ..................................................................................................................................
4.2.2 External system bus space ..........................................................................................................
4.2.3 Internal I/O space ........................................................................................................................
4.2.4 DRAM space ...............................................................................................................................
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