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參數(shù)資料
| 型號： | UPD16879GS-BGG |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅(qū)動電路 |
| 文件頁數(shù)： | 2/32頁 |
| 文件大?。?/td> | 199K |
| 代理商： | UPD16879GS-BGG |
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Data Sheet S14188EJ1V0DS00
2
μ
PD16879
ABSOLUTE MAXIMUM RATINGS (T
A
= +25°C)
When mounted on a glass epoxy board (100 mm
×
100 mm
×
1 mm, 15% copper foil)
Parameter
Symbol
Conditions
Rating
Unit
V
DD
Control part
–0.5 to +6.0
V
Supply voltage
V
M
Output part
–0.5 to +11.2
V
Input voltage
V
IN
–0.5 to V
DD
+ 0.5
V
Reference voltage
V
REF
External input
0.5
V
I
M(DC)
DC
±
0.15
A/ch
H bridge drive current
I
M(pulse)
PW < 10 ms, Duty < 5 %
±
0.3
A/ch
Power consumption
P
T
1.0
W
Peak junction temperature
T
CH(MAX)
150
°
C
Storage temperature
T
stg
–55
～
+150
°
C
RECOMMENDED OPERATING RANGE (T
A
= +25°C)
When mounted on a glass epoxy board (100 mm
×
100 mm
×
1 mm, 15% copper foil)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
DD
Control part
2.7
5.5
V
Supply voltage
V
M
Output part
4.0
11
V
Input voltage
V
IN
0
V
DD
V
Reference voltage
V
REF
External input
225
250
275
mV
EXP pin input voltage
V
EXPIN
V
DD
V
EXP pin input current
I
EXPIN
100
μ
A
I
M(DC)
DC
0.1
+0.1
A/ch
H bridge drive current
I
M(pulse)
P
W
< 10 ms, Duty < 5%
0.2
+0.2
A/ch
Clock frequency (OSC
IN
)
f
CLK
C
OSC
= 68 pF, V
REF
= 250 mV
3.9
4.5
6.0
MHz
Clock frequency amplitude
V
fCLK
0.7
×
V
DD
V
DD
V
Serial clock frequency
f
SCLK
5.0
MHz
Video sync signal width
PW
(VD)
f
CLK
= 4.5 MHz
250
ns
LATCH signal wait time
t
(VD-LATCH)
400
ns
SCLK wait time
t
(SCLK-LATCH)
400
ns
SDATA setup time
t
setup
80
ns
SDATA hold time
t
hold
Refer to Fig. 1
80
ns
Reset signal pulse width
t
RST
100
μ
s
Operating temperautre
T
A
10
85
°
C
Peak junction temperature
T
CH(MAX)
125
°
C
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