參數(shù)資料
型號： UPD16879GS-BGG
廠商： NEC Corp.
英文描述： MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT
中文描述： 單片四H橋驅動電路
文件頁數(shù)： 11/32頁
文件大?。?/td> 199K
代理商： UPD16879GS-BGG
D
1
μ
P
T
RESET
V
D
V
D
LATCH
DATA
SCLK
OSC
OUT
Start point wait
(FF1)
Start point wait+
Start point magnetize wait
(FF2)
ENABLE OUT
Note 1
CHOPPING
EXP 0, 1
PULSE OUT
PULSE GATE
(FF3)
PULSE CHECK
Note 2
(FF7)
CHECK SUM
Note 3
SCLK
SDATA
1st byte
→
13th byte
(LSB)
Data is held at rising edge SCLK
D0
D1
D2
D3
D4
D5
D6
D7
Initialization
S1
S2
S3
S4
pulse 0
S5
PS
S6
PS
S7
release PS
S8
S9
Enable
S10
release PS
S11
S12
data error
S13
normal data
S14
S3
S1
S2
S2
S3
S4
S4
S4
S7
S8
S8
S9
S9
S10
S10
S11
S11
S12
S12
S13
S13
S14
H level fixation
It reverts from the VD
start after a PS release.
L level fixation
L level fixation
Stop from
LATCH
↓
Start from
LATCH
↓
EXP can be change in PS period too.
Output L level
S13
S11
S10
S9
S8
S2
S3
S5 to S7
Pulse is nothing
because
Pulse count is done
Pulse is nothing
Notes 1.
2.
3.
ENABLE is set at the falling edge of FF1 when the level changes from
low to high, and at the falling edge of FF2 when the level changes from
high to low.
FF7 is an output signal that is used to check for the presence or
absence of a pulse in the serial data, is updated at the falling edge of
LATCH and reset once at the rising edge of LATCH. If CHECK SUM
is other than "00h", FF7 goes low, inhibiting pulse output, even if a
pulse is generated.
CHECK SUM output is updated at the falling edge of LATCH.
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PDF描述
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