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參數(shù)資料
| 型號： | UPD16879GS-BGG |
| 廠商： | NEC Corp. |
| 英文描述： | MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT |
| 中文描述： | 單片四H橋驅動電路 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大小： | 199K |
| 代理商： | UPD16879GS-BGG |
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Data Sheet S14188EJ1V0DS00
19
μ
PD16879
[2nd byte]
The 2nd byte specifies the delay between the first point wait time being cleared and the output pulse being
generated. This time called the first point magnetize wait time, and the output pulse is generated from the point at
which the start up wait time. The first point magnetize wait time is counted at the falling edge of the first point wait
time. The first point magnetize wait time can be set to 58.03 ms (when a 4.5 MHz clock input) and can be fine-tuned
by means of 8-bit division (227.6
μ
s step: with 4.5 MHz clock).
Always input data other than “0” to this byte because the first point magnetize wait time is necessary for latching
data. If “0” is input to this byte, data cannot be updated.
Table 4. 2nd Byte Data Configuration
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Data
First point wait
Data
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
00000000
Prohibition
MSB
LSB
00101001
About 9.33 ms
11111111
About 58.03 ms
n
N
×
1024/4.5 MHz
[3rd byte]
The 3rd byte sets the chopping frequency and external extension pins (EXP0, EXP1).
The chopping frequency sets by bits D0 to D5.
The EXP pins goes low (current sink) when the input data is “0”, and high (high-impedance state) when the input
data is “1”. Pull this pin up to V
DD
for use.
Table 5. 3rd Byte Data Configuration
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Data
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
EXP1 sets
MSB
LSB
EXP0 sets
Chopping frequency sets
D7: EXP1 sets
“1”: High impedance
“0”: Low level (Current sink)
D6: EXP0 sets
“1”: High impedance
“0”: Low level (Current sink)
The chopping frequency is set to 0 kHz and to a value in the range of 35.71 kHz to 225 kHz (4.5 MHz clock input).
Refer to table 1 (4 page).
[4th byte]
The 4th byte selects a parameter to be output EXT
α
and EXT
β
pins (logic operation monitor pin). And, power
save mode sets too.
Table 6. 4th Byte Data Configuration
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Data
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
Power save sets
Test parameter select
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