
1999 May 10
8
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end
receiver circuit
UAA1570HL
LIMINP
29
1.696
3.999
Positive limiter input:
AC couple this pin to the second IF filter
output or to ground if unused with single-ended filter
applications. The DC voltage is approximately 1 V below the
V
CCA(LIM)
supply on pin 31.
No DC coupling.
Positive limiter input DC feedback loop decoupling:
AC couple this pin to ground in close proximity to the pin.
The DC voltage is approximately 1 V below the V
CCA(LIM)
supply
on pin 31.
No DC coupling.
Limiter, sample clock squaring and sampler Emitter
Coupled Logic (ECL) circuits power supply:
decouple in
close proximity to pins 26 and 31. If present, isolate from the
common V
CC
line sourcing the first and second mixer by placing
a large decoupling capacitor between this block and the mixers.
Serial interface data input:
this DC-coupled CMOS
DATA
input
accepts 20-bit programming words into the synthesizer data
input register, while the
STROBE
is LOW, on the rising edge of
the
CLOCK
input. A DC short-circuit to ground is recommended
with the default frequency plan.
SIGN bit TTL output driver power supply:
critically isolate and
separately decouple this digital V
DDD
supply from all other
analog (V
CCA
) supplies. Maintain minimum trace lengths to
decoupling components. Particular attention should be applied to
prevent coupling into V
CCA(LIM)
pin 31. If SAA1575HL is used,
use the digital supply from the back-end.
Amplitude and time quantized second IF output signal:
extreme care should be taken to isolate this sampled TTL output
signal from all analog traces and components, particularly the
second IF filter components at the limiter input. Avoid coupling
into the reference oscillator signal trace.
SIGN bit TTL output driver sink ground:
critically isolate this
digital supply ground from all other analog supplies and grounds.
Maintain minimum trace lengths to decoupling components.
Synthesizer power supply:
decouple in close proximity to
pin 38
Sample clock squaring input:
accepts LOW-level AC coupled
sample clock inputs directly from the PLL reference oscillator or
DC-coupled externally squared digital clocks derived from the
PLL reference oscillator after external frequency division. The
maximum DC-coupled input level at pin 37 should not exceed
75% of the V
CCA(LIM)
supply value. The threshold level is set at
half the supply value on V
CCA(LIM)
pin 31.
PLL ground:
minimize ground inductance; use close proximity
decoupling to the V
CCA(PLL)
supply pin 36
this pin provides additional RF/IF shielding and has to be
connected to ground
BFCP
30
1.696
3.999
V
CCA(LIM)
31
2.7
5
DATA
32
CMOS level
CMOS level
V
DDD
33
2.7
(independent
of V
CC
level)
5
(independent
of V
CC
level)
SIGN
34
TTL output
TTL output
DGND
35
0
0
V
CCA(PLL)
36
2.7
5
SCLK
37
1.34
2.5
PLLGND
38
0
0
P39GND
39
0
0
SYMBOL
PIN
PIN VOLTAGE
TYPICAL VALUES (V)
DESCRIPTION
V
CC
= 2.7 V
V
CC
= 5 V