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參數(shù)資料
| 型號(hào)： | UAA1570HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Global Positioning System (GPS)baseband processor(通用定位系統(tǒng)基帶處理器) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | PLASTIC, SOT-313, LQFP-48 |
| 文件頁數(shù)： | 31/76頁 |
| 文件大?。?/td> | 890K |
| 代理商： | UAA1570HL |
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1999 May 10
31
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end
receiver circuit
UAA1570HL
7.7
Second IF filter
The second IF filter provides five functions:
1.
It provides selectivity to protect the limiter input from
spurious signals which pass through the first IF
band-pass filter envelope, typically 5 MHz wide.
2.
The filter attenuates undesired second mixer output
products, such as the LO leak, to levels which will not
block/capture the following limiter stage.
3.
The filter defines and shapes the noise bandwidth to
be amplitude quantized.
4.
It can provide impedance matching/transformation
from the IF mixer output to the limiter input while
maintaining stability.
5.
It can reject spurious common mode and/or differential
signals generated by high level local sources such as
harmonics of the reference clock or sample clock and
digital processing noise from associated devices such
as the SAA1575HL.
The second IF can be structured to support a wide range
of single-ended or balanced filters including LC or ceramic
realizations. The available system gain can provide
second IF signal levels sufficient to accommodate high
second IF filter losses.
The Philips application board again uses a 6th-order
coupled resonator filter based on the butterworth
response. The design method is described in the
“Handbook of FILTER SYNTHESIS”by Anatol Zverev.
Initially a skewed centre frequency and bandwidth were
input at 3.1 and 1.75 MHz, respectively, to help overcome
the asymmetry which is intrinsic in geometric low
frequency band-pass filter designs as they approach DC.
The following table design 3 dB down k and q parameters
were used:
R
s
= 548
R
L
= 996
q
0
= 20.0; insertion loss = 0.958; q
1
= 0.8041;
q
n
= 1.4156; k
12
= 0.7687; k
23
= 0.6582.
This filter was originally mirrored by a virtual ground to
convert it to a balanced form, but later the balanced
components were converted back to a single-ended form
(to reduce component count) simply by placing the
balanced series capacitors in series on one side of the
filter (effectively halving the capacitance value) and
grounding the opposite side of the tanks where these
series capacitors were removed. This effectively maintains
the differential power gain while only using a single-sided
output.
The filter was then resimulated in ‘PSPICE’ to optimize
against available discrete surface mount component
values. Finally the filters input and output direction were
reversed to ensure that the highest impedance side was
placed at the mixer output to maximize the available power
developed. A 909
termination was used at the output of
the filter to terminate the 4.87 k
limiter input. This
effective 766
termination is somewhat lower than the
initial design value of 2
×
548
or 1096
and therefore
develops approximately
1.56 dB less power with respect
to second mixer loading. The reduction of the impedance
level by 30% (or a factor of 0.7) was done in order to have
a large safety margin against instability of the
limiter/quantizer path. Instability can be caused here by
the large small-signal gain associated with this signal path
in conjunction with the high signal levels present at the
SIGN output. Furthermore, due to the strong
non-linearities present in this signal path, LO2 leakage in
conjunction with the IF2 itself can produce signals at the
IF1 frequency and thus enter the IF1 filter together with the
wanted signal. This impedance level reduction is passed
through the second IF filter and consequently lowers the
mixer 2 conversion gain by approximately 30%, too.
The filter design was determined to be sufficiently tolerant
to this adjustment by observing the effect on the filter’s
output noise response with respect to unstable peaking
and maintaining the desired selectivity response. Care
must be taken not to induce instability while observing the
IF2 filter noise response by using a 10 : 1 divider in
conjunction with a very low capacitance RF FET probe
(<0.5 pF).
In the default application, R323/305 in conjunction with the
equivalent parallel resistance at the respective filter input
and output give the desired terminating impedance.
The frequency of the mixed down third harmonic of the
reference oscillator is usually the most significant spurious
product which is generated in the default frequency plan
and must be kept at least 13 dB below the integrated noise
response of the filter. For example, typical true power
noise densities (Dn) for a nominal GPS demonstration
board operating at 3 V are expected to be approximately
100 dBm/Hz differential at the input of the limiter and
reflect the importance of designing a well matched RF
system. Assuming that a somewhat lower gain variation
has been realized with a noise density of approximately
105 dBm/Hz over an estimated 2 MHz noise equivalent
bandwidth, it is possible to evaluate and measure the
associated spurious product level that would result in a
13 dB jammer-to-noise (J/N) and 0.2 dB system noise
figure degradations as follows:
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