參數(shù)資料
型號： UAA1570HL
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡
英文描述： Global Positioning System (GPS)baseband processor(通用定位系統(tǒng)基帶處理器)
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP48
封裝： PLASTIC, SOT-313, LQFP-48
文件頁數(shù)： 37/76頁
文件大小： 890K
代理商： UAA1570HL
1999 May 10
37
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end
receiver circuit
UAA1570HL
7.9.2
M
AIN SYNTHESIZER DIVIDERS
(N-
PATH
)
The main synthesizer divider path includes an additional
fixed divide-by-3 prescaler preceding a programmable
variable N-divider which can be programmed over a range
from 64 to 127. The output of the programmable divider
passes through a fixed divide-by-2 and finally an optional
divide-by-1 or divide-by-2 before being applied to the
phase frequency detector.
7.9.3
S
ECOND LOCAL OSCILLATOR DIVIDERS
(L-
PATH
)
The second LO signal is divided down from the VCO
prescaler output, first by a programmable L-divider and
then by a fixed divide-by-2 before being buffered and
applied to the second mixer.
7.9.4
R
EFERENCE DIVIDERS
(R-
PATH
)
After squaring (limiting), the reference signal is divided
down first by a variable R-divider. The divide ratio ranges
from 4 to 31. The variable divider is followed by an optional
divide-by-1 or divide-by-2 before being applied to the
phase/frequency detector.
7.10
Serial interface
The three-wire serial bus consists of DC-coupled DATA,
CLOCK and STROBE CMOS level inputs. The DATA input
loads serial 20-bit programming words into the synthesizer
data input register on each rising edge of the CLOCK
input, while the strobe line is held LOW.
The CLOCK signal should be set-up HIGH for at least
30 ns before the STROBE state is changed.
Each DATA bit should be set-up for at least 30 ns before
being clocked into the register and then held for at least
30 ns. The CLOCK rate should not exceed 10 MHz and
the CLOCK pulse width should be at least 30 ns.
The 20-bit DATA word definition follows in the order in
which they are to be read (clocked) into the DATA register.
7.10.1
p0
AND
p1
The first bit read into the synthesizer should be the
power-down bit, p1, which enables one of two power-down
states if set HIGH. The second bit read into the register,
p0, defines the type of power-down. A complete
power-down of the UAA1570HL is performed if this bit is
set HIGH and a partial power-down with the synthesizer
remaining on if this bit is set LOW. For normal operation of
the UAA1570HL both of these bits are set LOW, which are
also the default values for p0,p1 = 0,0. The final
p0,p1 = 1,0 state is undefined.
7.10.2
r5
Next a post reference scaler bit, r5, is set to program a
divide-by-1 or divide-by-2 following the variable reference
divider. With this bit set LOW the divide-by-2 post scaler is
enabled and the phase frequency detector receives equal
mark/space ratio reference port signals. This is the default
state for this bit (r5 = 0). In the HIGH state the mark/space
ratio is a function of the variable reference divider value,
and the range of the reference divider is extended to lower
division ratios.
7.10.3
r0, r1, r2, r3
AND
r4
The next five bits clocked into the DATA register are the
binary equivalent value of the variable reference divider
ratio. The programmable range of this divider is
4 to 31
,
continuous
. The default value is set to 4
(r0, r1, r2, r3, r4 = 0, 0, 1, 0, 0) with the Most Significant
Bit (MSB) clocked into the DATA register first. The total
reference division ratio is set by these five bits if r5 is set
to the HIGH state. The range can be optionally doubled to
even values from 8 to 62
if r5 is set LOW. This option is
set in the default case, resulting in equal mark/space ratios
as described above. The total default reference division
ratio is therefore 8 with
(r0, r1, r2, r3, r4, r5 = 0, 0, 1, 0, 0, 0).
7.10.4
n7
As in the reference divider case the main synthesizer
divider includes an optional post scaler divider following
the main programmable divider. This divide-by-1 or
divide-by-2 is controlled by program word bit n7. With this
bit set LOW the divide-by-2 post scaler is enabled and the
phase frequency detector receives equal mark/space ratio
signals at its main synthesizer port. The default state for
this bit is (n7 = 1) which does NOT double the total main
synthesizer divide ratio as described below.
7.10.5
n0, n1, n2, n3, n4, n5
AND
n6
The next seven bits clocked into the DATA register are the
binary equivalent value of the variable main synthesizer
divider ratio. The programmable range of this divider is
64 to 127
,
continuous
. The default value is set to 71
(n0, n1, n2, n3, n4, n5, n6 = 1, 1, 1, 0, 0, 0, 1) with the
MSB clocked into the DATA register first. The output of the
main programmable divider includes a fixed divide-by-2
which modifies the previous range to all
even
values from
128 to 254
, inclusive. The programmable portion of the
main synthesizer division ratio is set by these seven bits if
n7 is set to the HIGH state as described above for the
default case.
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