參數(shù)資料
型號(hào)： UAA1570HL
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Global Positioning System (GPS)baseband processor(通用定位系統(tǒng)基帶處理器)
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP48
封裝： PLASTIC, SOT-313, LQFP-48
文件頁(yè)數(shù)： 33/76頁(yè)
文件大?。?/td> 890K
代理商： UAA1570HL
1999 May 10
33
Philips Semiconductors
Product specification
Global Positioning System (GPS) front-end
receiver circuit
UAA1570HL
7.8
Time and amplitude quantization
After frequency conversion in the double-superheterodyne
portion of the UAA1570HL and filtering to approximately a
2 MHz bandwidth in the second and final IF filter, the
frequency translated thermal noise from the GPS
pass-band around the L1 carrier is ready to be converted
to a digital signal for processing by the companion GPS
chip-set part (SAA1575HL). First the thermal noise’s sign
is determined by amplitude quantization in a 1-bit hard
limiter. This asynchronous information is then time
quantized by latching in a master/slave D-flip-flop to
complete the analog-to-digital conversion process. Finally,
this ECL digital SIGN bit data is translated to TTL levels
and sent to the SAA1575HL.
Four differential stages are used to hard limit the thermal
noise in the final IF. The total gain is approximately
63.9 dBV with a bandwidth of roughly 66 MHz and a noise
figure of approximately 11.3 dB in a 1 k
environment.
The parallel equivalent differential input impedance of the
limiter is 4.87 k
in parallel with 0.3 pF. Offset control is
provided through 42.5 k
feedback resistors from each
balanced output back to the inputs. External decoupling
capacitors cut the feedback loop for AC signals.
Limiter inputs as low as 25
μ
V (peak value differential) are
resolved at the output master flip-flop DFF1 in its
transparent mode. As the master flip-flop is latched
positive feedback resolves metastable states. While the
master flip-flop is in its transparent state the positive
feedback in the slave flip-flop will resolve the remaining
metastable states as it is latched.
Three forms of LO leakage can block the limiter if they
capture the device.
The first is LO leakage from the first mixer output which will
couple into the package die pad through internal 4 pF
common mode capacitors at the output of the 1st mixer.
This leakage signal is effectively filtered at the 2nd IF filter
output, but reappears internally on all down-bonded
grounds. It appears at a level of approximately 0.5 mV
(peak value differential) across the limiter input transistor
bases with an assumed 1st mixer input RF offset of
approximately 1 mV.
The second is LO leakage from the second mixer.
Assuming 1.5 mV RF input offset, the leakage at the
output of the second IF filter is expected to be
approximately 500
μ
V (peak value differential) (
69 dBm
into 1 k
) and sets the worst case nominal process
blocking level. With a nominal
50 dBm IF thermal level at
this point there is a 19 dB margin to blocking. To prevent
blocking, IF filter losses should be minimized and the
selectivity of the single-ended or differential second IF filter
has to be designed and characterized to maintain this
leakage product at least 11 dB below the integrated
second IF filter thermal noise signal.
The third form of blocking can occur if LO1 leakage is
sufficiently high (greater than 15 mV (peak value) on the
die pad) to be injected into the 2nd mixer regulators and all
down-bonded IF grounds. This results in burst of LO1
leakage at the 2nd mixer LO2 zero transition points which
increase LO2 leakage peaks by factors of 10.
The gain response of the limiter from a low impedance
source with no input strays is illustrated from the input to
the output of each stage in Fig.23.
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