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參數(shù)資料
| 型號： | TSB41LV03PFP |
| 英文描述： | IC APEX 20KE FPGA 600K 652-BGA |
| 中文描述： | 收發(fā)器 |
| 文件頁數(shù)： | 37/50頁 |
| 文件大?。?/td> | 662K |
| 代理商： | TSB41LV03PFP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
37
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
status transfer (continued)
The sequence of events for a status transfer is as follows:
1
a.
Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along
with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle). Normally
(unless interrupted by a receive operation), a status transfer is either 2 or 8 cycles long. A 2-cycle (4 bit)
transfer occurs when only status information is to be sent. An 8-cycle (16 bit) transfer occurs when
register data is to be sent in addition to any status information.
b.
Status transfer terminated. The PHY normally terminates a status transfer by asserting idle on the CTL
lines. The PHY may also interrupt a status transfer at any cycle by asserting receive on the CTL lines
to begin a receive operation. The PHY asserts at least one cycle of idle between consecutive status
transfers.
receive
Whenever the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting
receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates
the start of a packet by placing the speed code (encoded as shown in Table 20) on the D terminals, followed
by packet data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet has
been transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received
packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included
in the calculation of CRC or any other data protection mechanisms.
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed
by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds
the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any
data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D
terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all cases,
in normal operation, the TSB41AB3 sends at least one data-on indication before sending the speed code or
terminating the receive operation.
The TSB41AB3 also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization,
to the LLC. This packet it transferred to the LLC just as any other received self-ID packet.
00
00
10
XX
dn
d0
SPD
(a)
(b)
FF (Data-On)
D0
–
D7
CTL0, CTL1
SYSCLK
(c)
(d)
(e)
NOTE A: SPD = Speed code (see Table 20), d0
–
dn = Packet data
00
01
Figure 18. Normal Packet Reception Timing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
| TSC695F | IC,FPGA,57120-CELL,CMOS,BGA,1020PIN,PLASTIC |
| TSC695FL | IC,FPGA,79040-CELL,CMOS,BGA,1020PIN,PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41LV03PFP WAF | 制造商:Texas Instruments 功能描述: |
| TSB41LV04A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41LV04APFP | 功能描述:總線收發(fā)器 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| TSB41LV04APFPG4 | 功能描述:1394 接口集成電路 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41LV06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER |
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