參數(shù)資料
型號(hào)： TSB41LV03PFP
英文描述： IC APEX 20KE FPGA 600K 652-BGA
中文描述： 收發(fā)器
文件頁(yè)數(shù)： 19/50頁(yè)
文件大?。?/td> 662K
代理商： TSB41LV03PFP
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
internal register configuration (continued)
Table 4. Page 0 (Port Status) Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
AStat
2
Rd
TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:
Code
Arb Value
11
Z
01
1
10
0
00
invalid
BStat
2
Rd
TPB line state. This field indicates the TPB line state of the selected port. This field has the same encoding as
the Astat field.
Ch
1
Rd
Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected port is the
parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch bit is invalid after a
bus-reset until tree-ID has completed.
Con
1
Rd
Debounced port connection status. This bit indicates that the selected port is connected. The connection must
be stable for the debounce time of approximately 341 ms for the con bit to be set to 1. The con bit is reset to 0 by
hardware reset and is unaffected by bus-reset.
NOTE: The con bit indicates that the port is physically connected to a peer PHY, but the port is not necessarily
active.
Bias
1
Rd
Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable bias.
The incoming cable bias must be stable for the debounce time of 52
μ
s for the bias bit to be set to 1.
Port disabled control. If 1, the selected port is disabled. The dis bit is reset to 0 by hardware reset (all ports are
enabled for normal operation following hardware reset). The dis bit is not affected by bus-reset.
Dis
1
Rd/Wr
Peer_Speed
3
Rd
Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the selected
port, encoded as follows:
Code
Peer Speed
000
S100
001
S200
010
S400
011
–
111
invalid
The Peer_Speed field is invalid after a bus-reset until self-ID has completed.
NOTE: Peer speed codes higher than 010b (S400) are defined in 1394a-2000. However, the TSB41AB3 is only
capable of detecting peer speeds up to S400.
PIE
1
Rd/Wr
Port event interrupt enable. When set to 1, a port event on the selected port sets the port event interrupt (PEI) bit
and notify the link. This bit is reset to 0 by a hardware reset, and is unaffected by bus-reset.
Fault
1
Rd/Wr
Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that the port
is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming cable bias from
its attached peer. A suspend-fault occurs when a suspending port continues to detect incoming cable bias from
its attached peer. Writing 1 to this bit clears the fault bit to 0. This bit is reset to 0 by hardware reset and is
unaffected by bus-reset.
相關(guān)PDF資料
PDF描述
TSB41AB2I IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB41LV03PFP WAF 制造商:Texas Instruments 功能描述:
TSB41LV04A 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER
TSB41LV04APFP 功能描述:總線收發(fā)器 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
TSB41LV04APFPG4 功能描述:1394 接口集成電路 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB41LV06 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
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