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參數(shù)資料
| 型號： | TSB41LV03PFP |
| 英文描述： | IC APEX 20KE FPGA 600K 652-BGA |
| 中文描述： | 收發(fā)器 |
| 文件頁數(shù)： | 29/50頁 |
| 文件大?。?/td> | 662K |
| 代理商： | TSB41LV03PFP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
29
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
crystal selection (continued)
C10
X1
C9
Figure 12. Recommended Crystal and Capacitor Layout
It is strongly recommended that part of the verification process for the design be to measure the frequency of
the SYSCLK output of the PHY. This must be done with a frequency counter with an accuracy of six digits or
better. If the SYSCLK frequency is more than the crystal
’
s tolerance from 49.152 MHz, the load capacitance
of the crystal may be varied to improve frequency accuracy. If the frequency is too high, add more load
capacitance; if the frequency is too low, decrease load capacitance. Typically, changes are done to both load
capacitors (C9 and C10 in Figure 12) at the same time, and both must be of the same value. Additional design
details and requirements may be provided by the crystal vendor.
bus reset
In the TSB41AB3, the initiate bus reset (IBR) bit may be set to 1 in order to initiate a bus reset and initialization
sequence. The IBR bit, the root-holdoff (RHB) bit, and the gap-count register are located in PHY register 1 as
required by the 1394a-2000 Supplement (this configuration also maintains compatibility with older TI PHY
designs which were based upon the suggested register set defined in Annex J of IEEE Std 1394-1995).
Therefore, whenever the IBR bit is written, the RHB bit and gap-count are also necessarily written.
The RHB bit and gap-count may also be updated by PHY-config packets. The TSB41AB3 is 1394a-2000
compliant, and therefore both the reception and transmission of PHY-config packets cause the RHB and
gap-count to be loaded, unlike older IEEE Std 1394-1995 compliant PHYs which decode only received
PHY-config packets.
The gap-count is set to the maximum value of 63 after two consecutive bus resets without an intervening write
to the gap-count, either by a write to PHY register 1 or by a PHY-config packet. This mechanism allows a
PHY-config packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have
updated their RHB bits and gap-count values, without having the gap-count set back to 63 by the bus reset. The
subsequent connection of a new node to the bus, which initiates a bus reset, then causes the gap-count of each
node to be set to 63. Note, however, that if a subsequent bus reset is instead initiated by a write to register 1
to set the IBR bit, all other nodes on the bus have their gap-count values set to 63, while this node
’
s gap-count
remains set to the value just loaded by the write to PHY register 1.
Therefore, in order to maintain consistent gap-counts throughout the bus, the following rules apply to the use
of the IBR bit, RHB bit, and gap-count in PHY register 1:
Following the transmission of a PHY-config packet, a bus reset must be initiated in order to verify that all
nodes have correctly updated their RHB bits and gap-count values and to ensure that a subsequent new
connection to the bus causes the gap-count to be set to 63 on all nodes in the bus. If this bus reset is initiated
by setting the IBR bit to 1, the RHB bit and gap-count register must also be loaded with the correct values
consistent with the just transmitted PHY-config packet. In the TSB41AB3, the RHB bit and gap-count is
updated to their correct values upon the transmission of the PHY-config packet, and so these values may
first be read from register 1 and then rewritten.
Other than to initiate the bus reset, which must follow the transmission of a PHY-config packet, whenever
the IBR bit is set to 1 in order to initiate a bus reset, the gap-count value must also be set to 63 to be
consistent with other nodes on the bus. The RHB bit must be maintained with its current value.
The PHY register 1 is not written to except to set the IBR bit. The RHB bit and gap-count are not written
without also setting the IBR bit to 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
| TSC695F | IC,FPGA,57120-CELL,CMOS,BGA,1020PIN,PLASTIC |
| TSC695FL | IC,FPGA,79040-CELL,CMOS,BGA,1020PIN,PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41LV03PFP WAF | 制造商:Texas Instruments 功能描述: |
| TSB41LV04A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41LV04APFP | 功能描述:總線收發(fā)器 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| TSB41LV04APFPG4 | 功能描述:1394 接口集成電路 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41LV06 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER |
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