參數(shù)資料
型號(hào)： TSB41LV03PFP
英文描述： IC APEX 20KE FPGA 600K 652-BGA
中文描述： 收發(fā)器
文件頁(yè)數(shù)： 30/50頁(yè)
文件大?。?/td> 662K
代理商： TSB41LV03PFP
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
30
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
PHY-Link layer interface
The TSB41AB3 is designed to operate with an LLC such as the Texas Instruments TSB12LV21, TSB12LV22,
TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A. Details of operation for the
Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe
the operation of the PHY-LLC interface.
The interface to the LLC consists of the SYSCLK, CTL0
–
CTL1, D0
–
D7, LREQ, LPS, C/LKON, and ISO
terminals on the TSB41AB3, as shown in Figure 13.
ISO
ISO
C/LKON
LPS
SYSCLK
LREQ
D0
–
D7
CTL0
–
CTL1
Link
Layer
Controller
TSB41AB3
ISO
Figure 13. PHY-LLC Interface
The SYSCLK terminal provides a 49.152-MHz interface clock. All control and data signals are synchronized to,
and sampled on, the rising edge of SYSCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, that controls the flow of information and data
between the TSB41AB3 and LLC.
The D0
–
D7 terminals form a bidirectional data bus that is used to transfer status information, control information,
or packet data between the devices. The TSB41AB3 supports S100, S200, and S400 data transfers over the
D0
–
D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200 operation only the D0
–
D3
terminals are used; and in S400 operation all D0
–
D7 terminals are used for data transfer. When the TSB41AB3
is in control of the D0
–
D7 bus, unused Dn terminals are driven low during S100 and S200 operations. When
the LLC is in control of the D0
–
D7 bus, unused Dn terminals are ignored by the TSB41AB3.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY in order to request access
to the serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration.
The LPS and C/LKON terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC and may be used to reset the PHY-LLC interface or to disable SYSCLK.
The C/LKON terminal is used to send a wake-up notification to the LLC and to indicate an interrupt to the LLC
when either LPS is inactive or the PHY register L bit is zero.
The ISO terminal is used to enable the output differentiation logic on the CTL0
–
CTL1 and D0
–
D7 terminals.
Output differentiation is required when an isolation barrier of the type described in Annex J type isolation barrier
is implemented between the PHY and LLC.
The TSB41AB3 normally controls the CTL0
–
CTL1 and D0
–
D7 bidirectional buses. The LLC is allowed to drive
these buses only after the LLC has been granted permission to do so by the PHY.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB41LV03PFP WAF 制造商:Texas Instruments 功能描述:
TSB41LV04A 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER
TSB41LV04APFP 功能描述:總線收發(fā)器 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
TSB41LV04APFPG4 功能描述:1394 接口集成電路 Four-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB41LV06 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
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