參數(shù)資料
型號(hào)： TSB41BA3-EP
英文描述： IC APEX 20KE FPGA 400K 672-FBGA
中文描述： 軍事增強(qiáng)塑料的IEEE 1394b三端口電纜收發(fā)器/仲裁器
文件頁(yè)數(shù)： 8/50頁(yè)
文件大?。?/td> 662K
代理商： TSB41BA3-EP
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
FILTER0
FILTER1
TYPE
CMOS
NO.
71
72
I/O
PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter
required for stable operation of the internal frequency-multiplier PLL using the crystal oscillator. A
0.1-
μ
F
±
10% capacitor is the only external component required to complete this filter.
Link interface isolation control input. This terminal controls the operation of output differentiation
logic on the CTL and D terminals. If an optional isolation barrier of the type described in Annex J of
IEEE Std 1394-1995 is implemented between the TSB41AB3 and LLC, the ISO terminal is tied low to
enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus
holder isolation is implemented, the ISO terminal is tied high through a pullup to disable the
differentiation logic. For additional information see the TI application note
Serial Bus Galvanic
Isolation
, literature number SLLA011.
ISO
CMOS
26
I
LPS
CMOS
5 V tol
19
I
Link power status input. This terminal is used to monitor the active/power status of the link layer
controller and to control the state of the PHY-LLC interface. This terminal is connected either to the
VDD supplying the LLC through a 10-k
resistor, or to a pulsed output which is active when the LLC is
powered. A pulsed signal is used when an isolation barrier exists between the LLC and PHY (see
Figure 8).
The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6
μ
s (128
SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating
signal with a low time less than 2.6
μ
s). The LPS input must be high for at least 21 ns in order to be
observed as high by the PHY.
When the TSB41AB3 detects that LPS is inactive, it places the PHY-LLC interface into a low-power
reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ
input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more
than 26
μ
s (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in
which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled
state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1,
and is considered inactive if either the LPS input is inactive or the the LCtrl register bit is cleared to 0.
LREQ
CMOS
5 V tol
1
I
LLC request input. The LLC uses this input to initiate a service request to the TSB41AB3. Bus holder
is built into this terminal.
PC0
PC1
PC2
CMOS
23
24
25
I
Power class programming inputs. On hardware reset, these inputs set the default value of the power
class indicated during self-ID. Programming is done by tying the terminals high or low. See Table 9
for encoding.
PD
CMOS
5 V tol
18
I
Power-down input. A high on this terminal turns off all internal circuitry except the cable-active
monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal
pull-down on the RESET terminal must to force a reset of the internal control logic.
PLLGND
Supply
74, 75
–
PLL circuit ground terminals. These terminals should be tied together to a low-impedance point on
the circuit board ground plane.
PLLVDD
Supply
73
–
PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each
terminal are suggested, such as paralleled 0.1
μ
F and 0.001
μ
F. Lower frequency 10-
μ
F filtering
capacitors are also recommended. These supply terminals are separated from DVDD and AVDD
internal to the device to provide noise isolation. They must be tied at a low-impedance point on the
circuit board.
RESET
CMOS
78
I
Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to
VDD is provided so only an external delay capacitor is required for proper power-up operation (see
power-up reset
in the Application Information section). The RESET terminal also incorporates an
internal pulldown which is activated when the PD input is asserted high. This input is otherwise a
standard logic input, and can also be driven by an open-drain type driver.
R0
R1
Bias
66
67
–
Current setting resistor terminals. These terminals are connected to an external resistance to set the
internal operating currents and cable driver output currents. A resistance of 6.34 k
±
1% is required
to meet the IEEE Std 1394-1995 output voltage limits.
SE
CMOS
32
I
Test control input. This input is used in manufacturing test of the TSB41AB3. For normal use this
terminal is tied to GND through a 1-k
pulldown resistor.
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