- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382686 > TSB41BA3-EP IC APEX 20KE FPGA 400K 672-FBGA PDF資料下載
參數(shù)資料
| 型號： | TSB41BA3-EP |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 軍事增強塑料的IEEE 1394b三端口電纜收發(fā)器/仲裁器 |
| 文件頁數(shù)： | 38/50頁 |
| 文件大?。?/td> | 662K |
| 代理商： | TSB41BA3-EP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當(dāng)前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
38
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receive (continued)
The sequence of events for a normal packet reception is as follows:
1
a.
Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle when receive is asserted. However, the receive operation may
interrupt a status transfer operation that is in progress so that the CTL lines may change from status
to receive without an intervening idle.
Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more
cycles preceding the speed-code.
Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D
lines for one cycle immediately preceding packet data. The link decodes the speed code on the first
receive cycle for which the D lines are not the data-on code. If the speed code is invalid, or indicates
a speed higher that that which the link is capable of handling, the link should ignore the subsequent data.
Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet
data on the D lines with receive on the CTL lines for the remainder of the receive operation.
b.
c.
d.
e.
Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
00
00
10
XX
(a)
(b)
(c)
FF (Data-On)
D0
–
D7
CTL0, CTL1
SYSCLK
00
01
Figure 19. Null Packet Reception Timing
The sequence of events for a null packet reception is as follows:
1
a.
Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle when receive is asserted. However, the receive operation may
interrupt a status transfer operation that is in progress so that the CTL lines may change from status
to receive without an intervening idle.
b.
Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.
c.
Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
Table 20. Receive Speed Codes
D0
–
D7
00XX XXXX
0100 XXXX
0101 0000
1YYY YYYY
DATA RATE
S100
S200
S400
data-on indication
NOTE: X = Output as 0 by PHY, ignored by LLC.
Y = Output as 1 by PHY, ignored by LLC.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB41LV03PFP | IC APEX 20KE FPGA 600K 652-BGA |
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
| TSC695F | IC,FPGA,57120-CELL,CMOS,BGA,1020PIN,PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41BA3IPFP | 制造商:Rochester Electronics LLC 功能描述:1394B-2002 3-PORT PHYSICAL LAYER DEVICE - Bulk 制造商:Texas Instruments 功能描述:CBL TRNSCVR 6TR 6TX 6RX 80HTQFP - Trays |
| TSB41BA3PFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:CBL TRNSCVR 6TR 6TX 6RX 80HTQFP - Trays |
| TSB41LV01 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41LV01PAP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TSB41LV02 WAF | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。