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| 型號： | TSB41BA3-EP |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 軍事增強塑料的IEEE 1394b三端口電纜收發(fā)器/仲裁器 |
| 文件頁數(shù)： | 14/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41BA3-EP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of operating conditions (unless otherwise noted)
(continued)
thermal characteristics
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
R
θ
JA
Junction-to-ambient thermal resistance
Board mounted, no air flow, high conductivity TI
recommended test board chip soldered or greased to
recommended test board, chip soldered or greased to
thermal land with 2 oz. copper
19.04
°
C/W
R
θ
JC
Junction-to-case thermal resistance
0.17
°
C/W
R
θ
JA
Junction-to-ambient thermal resistance
Board mounted, no air flow, high conductivity TI
recommended test board with thermal land but no solder
or grease thermal connection to thermal land with 2 oz.
copper
31.52
°
C/W
R
θ
JC
Junction-to-case-thermal resistance
0.17
°
C/W
R
θ
JA
R
θ
JC
Junction-to-ambient thermal resistance
Junction-to-case-thermal resistance
Board mounted, no air flow, high conductivity JEDEC test
board with 1 oz. copper
49.17
3.11
°
C/W
°
C/W
switching characteristics
PARAMETER
TEST CONDITION
MIN
TYP
MAX
±
0.15
±
0.1
1.2
UNIT
Jitter, transmit
Between TPA and TPB
ns
Skew, transmit
Between TPA and TPB
ns
tr
tf
tsu
th
td
Test Conditions: 3.3 VCC, TA
= 25
°
C
TP differential rise time, transmit
10% to 90%,
At 1394 connector
0.5
ns
TP differential fall time, transmit
90% to 10%,
At 1394 connector
0.5
1.2
ns
Setup time, CTL0, CTL1, D1
–
D7, LREQ to SYSCLK
50% to 50%,
See Figure 2
5
ns
Hold time, CTL0, CTL1, D1
–
D7, LREQ after SYSCLK
50% to 50%,
See Figure 2
2
ns
Delay time, SYSCLK to CTL0, CTL1, D1
–
D7
50% to 50%,
See Figure 3
2
ns
PARAMETER MEASUREMENT INFORMATION
TPAx+
TPBx+
TPAx
–
TPBx
–
56
Figure 1. Test Load Diagram
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