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| 型號(hào)： | TSB41BA3-EP |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 軍事增強(qiáng)塑料的IEEE 1394b三端口電纜收發(fā)器/仲裁器 |
| 文件頁數(shù)： | 42/50頁 |
| 文件大小： | 662K |
| 代理商： | TSB41BA3-EP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
42
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interface reset and disable (continued)
Table 21. LPS Timing Parameters
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
μ
s
μ
s
TLPSL
TLPSH
LPS low time (when pulsed) (see Note 5)
0.09
2.6
LPS high time (when pulsed) (see Note 5)
0.021
2.6
LPS duty cycle (when pulsed) (see Note 6)
20%
55%
TLPS_RESET
TLPS_DISABLE
TRESTORE
Time for PHY to recognize LPS deasserted and reset the interface
2.6
2.68
μ
s
Time for PHY to recognize LPS deasserted and disable the interface
26.03
26.11
23
μ
s
Time to permit optional isolation circuits to restore during an interface reset
15
μ
s
ns
TCLK_ACTIVATE
Time for SYSCLK to be activated from reassertion of LPS
PHY not in low-power state
60
PHY in low-power state
5.3
7.3
ms
The maximum value for TRESTORE does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before
LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less
than TLPS_DISABLE.
NOTES:
5. The specified TLPSL and TLPSH times are worst-case values appropriate for operation with the TSB41AB3. These values are broader
than those specified for the same parameters in the 1394a-2000 Supplement (i.e., an implementation of LPS that meets the
requirements of 1394a-2000 operates correctly with the TSB41AB3).
6. A pulsed LPS signal must have a duty cycle (ratio of TLPSH to cycle period) in the specified range to ensure proper operation when
using an isolation barrier on the LPS signal (e.g., as shown in Figure 8)
The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request
activity. When the PHY observes that LPS has been deasserted for T
LPS_RESET
, it resets the interface. When
the interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity
on the LREQ signal. The timing for interface reset is shown in Figure 22 and Figure 23.
SYSCLK
ISO
(Low)
(a)
(c)
(b)
CTL0, CTL1
D0
–
D7
LREQ
LPS
(d)
TLPS_RESET
TRESTORE
TLPSL
TLPSH
Figure 22. Interface Reset, ISO Low
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