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參數(shù)資料
| 型號： | TSB41BA3-EP |
| 英文描述： | IC APEX 20KE FPGA 400K 672-FBGA |
| 中文描述： | 軍事增強塑料的IEEE 1394b三端口電纜收發(fā)器/仲裁器 |
| 文件頁數(shù)： | 39/50頁 |
| 文件大?。?/td> | 662K |
| 代理商： | TSB41BA3-EP |
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SLLS418G
–
JUNE 2000
–
REVISED JANUARY 2003
39
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit
When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus.
If the PHY wins arbitration for the serial bus, the PHY-LLC interface bus is granted to the LLC by asserting the
grant state (11b) on the CTL terminals for one SYSCLK cycle, followed by idle for one clock cycle. The LLC then
takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless
the LLC is immediately releasing the interface, the LLC may assert the idle state for at most one clock before
it must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control
of the bus while it prepares data for transmission. The LLC may assert hold for zero or more clock cycles (i.e.,
the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time.
When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first
bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have
been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle, and then asserts
idle for one additional cycle before releasing the interface bus and putting the CTL and D terminals in a
high-impedance state. The PHY then regains control of the interface bus.
The hold state asserted at the end of packet transmission indicates to the PHY that the LLC requests to send
another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation
request by waiting the required minimum packet separation time and then asserting grant as before. This
function may be used to send a unified response after sending an acknowledge, or to send consecutive
isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all
packets transmitted during a single bus ownership must be of the same speed (since the speed of the packet
is set before the first packet). If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is
set), the LLC must specify the speed code of the next concatenated packet on the D terminals when it asserts
hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the speed
code that precedes received packet data as given in Table 20.
After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the
CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling
idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC,
there is an extra clock period allowed so that both sides of the interface can operate on registered versions of
the interface signals.
相關PDF資料 |
PDF描述 |
|---|---|
| TSB41LV03PFP | IC APEX 20KE FPGA 600K 652-BGA |
| TSB41AB2I | IEEE 1394a-2000 TWO-PORT CABLE TRANSCEVER/ARBITER |
| TSB41LV03AI | IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSC692E | 672-pin FineLine BGA |
| TSC695F | IC,FPGA,57120-CELL,CMOS,BGA,1020PIN,PLASTIC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41BA3IPFP | 制造商:Rochester Electronics LLC 功能描述:1394B-2002 3-PORT PHYSICAL LAYER DEVICE - Bulk 制造商:Texas Instruments 功能描述:CBL TRNSCVR 6TR 6TX 6RX 80HTQFP - Trays |
| TSB41BA3PFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述:CBL TRNSCVR 6TR 6TX 6RX 80HTQFP - Trays |
| TSB41LV01 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394A ONE-PORT CABLE TRANSCEIVER/ARBITER |
| TSB41LV01PAP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TSB41LV02 WAF | 制造商:Texas Instruments 功能描述: |
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