- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2118 > TSB41AB3IPFPEP (Texas Instruments)IC 3PRT CABLE TXRX/ARBIT 80HTQFP PDF資料下載
參數(shù)資料
| 型號： | TSB41AB3IPFPEP |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 54/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 3PRT CABLE TXRX/ARBIT 80HTQFP |
| 標準包裝： | 96 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數(shù)： | 6/6 |
| 規(guī)程： | IEEE 1394 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應商設備封裝： | 80-HTQFP（12x12） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 882 (CN2011-ZH PDF) |
| 其它名稱： | 296-22528 V62/03612-01XE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁當前第54頁第55頁
TSB41AB3EP
IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS122C JULY 2002 REVISED JUNE 2008
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
TYPE
NO.
I/O
DESCRIPTION
FILTER0
FILTER1
CMOS
71
72
I/O
PLL filter terminals. These terminals are connected to an external capacitor to form a lag-lead filter
required for stable operation of the internal frequency-multiplier PLL running off of the crystal
oscillator. A 0.1-
F ± 10% capacitor is the only external component required to complete this filter.
ISO
CMOS
26
I
Link interface isolation control input. This terminal controls the operation of output differentiation
logic on the CTL and D terminals. If an optional isolation barrier of the type described in Annex J of
IEEE Std 1394-1995 is implemented between the TSB41AB3 and LLC, the ISO terminal is tied low to
enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI bus
holder isolation is implemented, the ISO terminal is tied high through a pullup to disable the
differentiation logic. For additional information see the TI application note Serial Bus Galvanic
Isolation, literature number SLLA011.
LPS
CMOS
5 V tol
19
I
Link power status input. This terminal is used to monitor the active/power status of the link layer
controller and to control the state of the PHY-LLC interface. This terminal is connected to either the
VDD supplying the LLC through a 10-k resistor, or to a pulsed output which is active when the LLC is
powered. A pulsed signal is used when an isolation barrier exists between the LLC and PHY (see
Figure 8).
The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6
s (128
SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating
signal with a low time less than 2.6
s). The LPS input must be high for at least 21 ns in order to be
observed as high by the PHY.
When the TSB41AB3 detects that LPS is inactive, it places the PHY-LLC interface into a low-power
reset state. In the reset state, the CTL and D outputs are held in the logic zero state and the LREQ
input is ignored; however, the SYSCLK output remains active. If the LPS input remains low for more
than 26
s (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power disabled state in
which the SYSCLK output is also held inactive. The PHY-LLC interface is placed into the disabled
state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1,
and is considered inactive if either the LPS input is inactive or the the LCtrl register bit is cleared to 0.
LREQ
CMOS
5 V tol
1
I
LLC request input. The LLC uses this input to initiate a service request to the TSB41AB3. Bus holder
is built into this terminal.
PC0
PC1
PC2
CMOS
23
24
25
I
Power class programming inputs. On hardware reset, these inputs set the default value of the power
class indicated during self-ID. Programming is done by tying the terminals high or low. See Table 9
for encoding.
PD
CMOS
5 V tol
18
I
Power-down input. A high on this terminal turns off all internal circuitry except the cable-active
monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal
pull-down on the RESET terminal must to force a reset of the internal control logic.
PLLGND
Supply
74, 75
PLL circuit ground terminals. These terminals should be tied together to the low impedance circuit
board ground plane.
PLLVDD
Supply
73
PLL circuit power terminals. A combination of high-frequency decoupling capacitors near each
terminal are suggested, such as paralleled 0.1
F and 0.001 F. Lower frequency 10-F filtering
capacitors are also recommended. These supply terminals are separated from DVDD and AVDD
internal to the device to provide noise isolation. They must be tied at a low-impedance point on the
circuit board.
RESET
CMOS
78
I
Logic reset input. Asserting this terminal low resets the internal logic. An internal pullup resistor to
VDD is provided so only an external delay capacitor is required for proper power-up operation (see
power-up reset in the Application Information section). The RESET terminal also incorporates an
internal pulldown which is activated when the PD input is asserted high. This input is otherwise a
standard logic input, and can also be driven by an open-drain type driver.
R0
R1
Bias
66
67
Current setting resistor terminals. These terminals are connected to an external resistance to set the
internal operating currents and cable driver output currents. A resistance of 6.34 k
±1% is required
to meet the IEEE Std 1394-1995 output voltage limits.
SE
CMOS
32
I
Test control input. This input is used in manufacturing test of the TSB41AB3. For normal use this
terminal is tied to GND through a 1-k
pulldown resistor.
相關PDF資料 |
PDF描述 |
|---|---|
| TVP5150APBSRG4 | IC VIDEO DECODER 8BIT 32TQFP |
| TVP5154AIPNP | IC VIDEO DECODER 4CH 128-HTQFP |
| TW2804-FE | IC NTSC/PAL VIDEO DECOD 128PQF |
| TW2809-BC1-GR | IC INTERFACE |
| TW2815-TA1-GR | IC A/V CODEC/DECOD 4CH 100TQFP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TSB41AB3IPFPG4 | 制造商:Texas Instruments 功能描述:THREE PORT CBL TRNSCVR/ARBITER 1TX 1RX 400MBPS 80HTQFP - Rail/Tube |
| TSB41AB3MPFPEP | 功能描述:1394 接口集成電路 Enh Product 3Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41AB3PFP | 功能描述:緩沖器和線路驅動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| TSB41AB3PFPG4 | 功能描述:1394 接口集成電路 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB41BA3 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE1394B THREE PORT CABLE TRANSCEIVER/ARBITER |
發(fā)布緊急采購，3分鐘左右您將得到回復。