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參數(shù)資料
| 型號(hào)： | TSB41AB3IPFPEP |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 36/55頁 |
| 文件大小： | 0K |
| 描述： | IC 3PRT CABLE TXRX/ARBIT 80HTQFP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 6/6 |
| 規(guī)程： | IEEE 1394 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 80-HTQFP（12x12） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 882 (CN2011-ZH PDF) |
| 其它名稱： | 296-22528 V62/03612-01XE |
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TSB41AB3EP
IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS122C JULY 2002 REVISED JUNE 2008
41
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit (continued)
00
10
(f)
(g)
(e)
(d)
(c)
(b)
(a)
01
00
11
dn
d0, d1, . . .
Link controls CTL and D
PHY High-Impedance CTL and D outputs
D0–D7
CTL0, CTL1
SYSCLK
NOTE A: SPD = Speed code, see Table 20 d0–dn = Packet data
00
01
00
SPD
Figure 21. Normal Packet Transmission Timing
The sequence of events for a normal packet transmission is as follows:1
a.
Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over
control of the interface to the link so that the link may transmit a packet. The PHY releases control of
the interface (i.e., it places its CTL and D outputs in a high-impedance state) following the idle cycle.
b.
Optional idle cycle. The link may assert at most one idle cycle preceding assertion of either hold or
transmit. This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.
c.
Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of transmit. These
hold cycle(s) are optional; the link is not required to assert hold preceding transmit.
d.
Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along
with the data on the D lines.
e.
Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle
on the CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in
order to transmit a concatenated packet. The link asserts idle to indicate that packet transmission is
complete and the PHY may release the serial bus. The link then asserts idle for one more cycle following
this cycle of hold or idle before releasing the interface and returning control to the PHY.
f.
Concatenated packet speed-code. If multispeed concatenation is enabled in the PHY, the link asserts
a speed code on the D lines when it asserts hold to terminate packet transmission. This speed code
indicates the transmission speed for the concatenated packet that is to follow. The encoding for this
concatenated packet speed-code is the same as the encoding for the received packet speed code (see
Table 20). The link may not concatenate an S100 packet onto any higher-speed packet.
g.
After regaining control of the interface, the PHY asserts at least one cycle of idle before any subsequent
status transfer, receive operation, or transmit operation.
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