參數(shù)資料
型號： TSB41AB3IPFPEP
廠商： Texas Instruments
文件頁數(shù)： 33/55頁
文件大小： 0K
描述： IC 3PRT CABLE TXRX/ARBIT 80HTQFP
標準包裝： 96
類型： 收發(fā)器
驅(qū)動器/接收器數(shù)： 6/6
規(guī)程： IEEE 1394
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 80-TQFP 裸露焊盤
供應商設(shè)備封裝： 80-HTQFP（12x12）
包裝： 托盤
產(chǎn)品目錄頁面： 882 (CN2011-ZH PDF)
其它名稱： 296-22528
V62/03612-01XE
TSB41AB3EP
IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER
SGLS122C JULY 2002 REVISED JUNE 2008
39
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receive (continued)
The sequence of events for a normal packet reception is as follows:1
a.
Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle when receive is asserted. However, the receive operation may
interrupt a status transfer operation that is in progress so that the CTL lines may change from status
to receive without an intervening idle.
b.
Data-on indication. The PHY may assert the data-on indication code on the D lines for one or more
cycles preceding the speed-code.
c.
Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D
lines for one cycle immediately preceding packet data. The link decodes the speed code on the first
receive cycle for which the D lines are not the data-on code. If the speed code is invalid, or indicates
a speed higher that that which the link is capable of handling, the link should ignore the subsequent data.
d.
Receive data. Following the data-on indication (if any) and the speed-code, the PHY asserts packet
data on the D lines with receive on the CTL lines for the remainder of the receive operation.
e.
Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
00
10
XX
(a)
(b)
(c)
FF (data-on)
D0–D7
CTL0, CTL1
SYSCLK
00
01
Figure 20. Null Packet Reception Timing
The sequence of events for a null packet reception is as follows:1
a.
Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL
lines. Normally, the interface is idle when receive is asserted. However, the receive operation may
interrupt a status transfer operation that is in progress so that the CTL lines may change from status
to receive without an intervening idle.
b.
Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.
c.
Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL
lines. The PHY asserts at least one cycle of idle following a receive operation.
Table 20. Receive Speed Codes
D0–D7
DATA RATE
00XX XXXX
S100
0100 XXXX
S200
0101 0000
S400
1YYY YYYY
data-on indication
NOTE: X = Output as 0 by PHY, ignored by LLC.
Y = Output as 1 by PHY, ignored by LLC.
相關(guān)PDF資料
PDF描述
TVP5150APBSRG4 IC VIDEO DECODER 8BIT 32TQFP
TVP5154AIPNP IC VIDEO DECODER 4CH 128-HTQFP
TW2804-FE IC NTSC/PAL VIDEO DECOD 128PQF
TW2809-BC1-GR IC INTERFACE
TW2815-TA1-GR IC A/V CODEC/DECOD 4CH 100TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB41AB3IPFPG4 制造商:Texas Instruments 功能描述:THREE PORT CBL TRNSCVR/ARBITER 1TX 1RX 400MBPS 80HTQFP - Rail/Tube
TSB41AB3MPFPEP 功能描述:1394 接口集成電路 Enh Product 3Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB41AB3PFP 功能描述:緩沖器和線路驅(qū)動器 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
TSB41AB3PFPG4 功能描述:1394 接口集成電路 Three-Port Cable Xcvr/Arbiter RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB41BA3 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE1394B THREE PORT CABLE TRANSCEIVER/ARBITER
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*