
www.ti.com
P
PCLK
2
1
3
4
4
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
6.10.1.6
VPFE Electrical Data/Timing
Table 6-35. Timing Requirements for VPFE PCLK Master/Slave Mode
(1)
(see
Figure 6-19
)
-400
-500
-600
MIN
NO.
UNIT
MAX
1
2
3
4
t
c(PCLK)
t
w(PCLKH)
t
w(PCLKL)
t
t(PCLK)
Cycle time, PCLK
Pulse duration, PCLK high
Pulse duration, PCLK low
Transition time, PCLK
10.204 or 13.33
(2)
ns
ns
ns
ns
0.4P
0.4P
TBD
(1)
(2)
P = PCLK period in ns.
When PCLK sources the clock for both the VPFE and VPBE, the minimum cycle time of 13.33 ns (specified in
Table 6-42
,
Timing
Requirements for VPBE CLK Inputs
for VPBE)
must
be met. When PCLK sources the clock for only the VPFE, a minimum cycle time of
10.2 ns may be used.
Figure 6-19. VPFE PCLK Timing
Table 6-36. Timing Requirements for VPFE (CCD) Slave Mode
(1)
(see
Figure 6-20
)
-400
-500
-600
NO.
UNIT
MIN
4.5
0.5
4.5
0.5
4.5
0.5
4.5
0.5
4.5
0.5
MAX
5
6
7
8
9
10
11
12
13
14
t
su(CCDV-PCLK)
t
h(PCLK-CCDV)
t
su(HDV-PCLK)
t
h(PCLK-HDV)
t
su(VDV-PCLK)
t
h(PCLK-VDV)
t
su(C_WEV-PCLK)
t
h(PCLK-C_WEV)
t
su(C_FIELDV-PCLK)
t
h(PCLK-C_FIELDV)
The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
Setup time, CCD valid before PCLK edge
Hold time, CCD valid after PCLK edge
Setup time, HD valid before PCLK edge
Hold time, HD valid after PCLK edge
Setup time, VD valid before PCLK edge
Hold time, VD valid after PCLK edge
Setup time, C_WE valid before PCLK edge
Hold time, C_WE valid after PCLK edge
Setup time, C_FIELD valid before PCLK edge
Hold time, C_FIELD valid after PCLK edge
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
Peripheral Information and Electrical Specifications
222
Submit Documentation Feedback