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TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
31
16
RESERVED
R-0000 0000 0000 0000
15
10
9
8
7
0
RESERVED
RESERVED
TIMOUT
R- 0000 00
R/W-00
R/W-1000 0000
LEGEND: R = Read; W = Write; -
n
= value after reset
Figure 3-8. HPICTL Register
Table 3-16. HPICTL Description
Bit
31:10
9:8
Field Name
RESERVED Reserved. Read-only, writes have no effect.
RESERVED Reserved. For proper device operation, the user should
only
write "0" to these bits (default).
Host Burst Write Timeout Value
When the HPI time-out counter reaches the value programmed here, the HPI write FIFO content is flushed. For
TIMOUT
more details on the time-out counter and its use in write bursting, see the
TMS320DM643x DMP Host Port
Interface (HPI)
User's Guide (literature number
SPRU998
).
Description
7:0
3.6.2.2
Timer Control Register (TIMERCTL)
The Timer Control Register (TIMERCTL) provides additional control for Timer0 and Timer2.
The user
should only modify this register once during device initialization, when the corresponding Timer is
not in use.
Timer 2 Control: The TIMERCTL.WDRST bit determines if the WatchDog timer event (Timer 2) can
cause a device max reset. For more details on the description of a maximum reset, see
Section 6.5.3
,
Maximum Reset
.
Timer 0 Control: The TINP0SEL bit selects the clock source connected to Timer0's TIN0 input.
31
16
RESERVED
R-0000 0000 0000 0000
15
2
1
0
TINP0
SEL
WD
RST
RESERVED
R- 0000 0000 0000 00
R/W-0
R/W-1
LEGEND: R = Read; W = Write; -
n
= value after reset
Figure 3-9. TIMERCTL Register
Table 3-17. TIMERCTL Description
Bit
31:2
Field Name
RESERVED Reserved. Read-Only, writes have no effect.
Timer0 External Input (TIN0) Select
0 = Timer0 external input comes directly from the TINP0L pin (
default
).
TINP0SEL
1 = Timer0 external input is TINP0L pin divided by 6. For example, if TINP0L = 27MHz, Timer0 input TIN0 is
27MHz / 6 = 4.5 MHz.
WatchDog Reset Enable
WDRST
0 = WatchDog Timer Event (WDINT from Timer2) does not cause device reset.
1 = WatchDog Timer Event (WDINT from Timer2) causes a device max reset (
default
).
Description
1
0
Device Configurations
100
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