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參數(shù)資料
| 型號： | TMX320DM6437BZWTA |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Digital Media Processor |
| 中文描述： | 數(shù)字媒體處理器 |
| 文件頁數(shù)： | 198/309頁 |
| 文件大?。?/td> | 2216K |
| 代理商： | TMX320DM6437BZWTA |
www.ti.com
P
6.7 Clock PLLs
6.7.1
PLL1 and PLL2
PLL
PWR18
C2
C1
EMI Filter
+1.8 V
0.01 F
DM643x
PLL2
PLL1
0.1 F
TMS320DM6437
Digital Media Processor
SPRS345B–NOVEMBER 2006–REVISED MARCH 2007
There are two independently controlled PLLs on DM6437. PLL1 generates the frequencies required for the
DSP, DMA, VPFE, and other peripherals. PLL2 generates the frequencies required for the DDR2 interface
and the VPBE in certain modes. The recommended reference clock for both PLLs is the 27-MHz crystal
input.
Both PLL1 and PLL2 power is supplied externally via the 1.8 V PLL power-supply pin (PLL
PWR18
). An
external EMI filter circuit
must
be added to PLL
PWR18
, as shown in
Figure 6-11
. The 1.8-V supply of the
EMI filter must be from the same 1.8-V power plane supplying the device’s 1.8-V I/O power-supply pins
(DV
DDDR2
). TI requires EMI filter manufacturer Murata, part number NFM18CC222R1C3.
All PLL external components (C1, C2, and the EMI Filter)
must
be placed as close to the device as
possible. For the best performance, TI recommends that all the PLL external components be on a single
side of the board without jumpers, switches, or components other than the ones shown in
Figure 6-11
. For
reduced PLL jitter, maximize the spacing between switching signals and the PLL external components
(C1, C2, and the EMI Filter).
Figure 6-11. PLL1 and PLL2 External Connection
The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,
see
Section 6.7.4
,
Clock PLL Electrical Data/Timing (Input and Output Clocks)
.
There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating
frequency for MXI/CLKIN, PLLOUT, and the device clocks (SYSCLKs). The PLL Controllers
must
be
configured not to exceed any of these constraints documented in this section (certain combinations of
external clock inputs, internal dividers, and PLL multiply ratios might not be supported). For these
constraints (ranges), see
Table 6-14
through
Table 6-16
.
Table 6-14. PLL1 and PLL2 Multiplier Ranges
PLL MULTIPLIER (PLLM)
PLL1 Multiplier
PLL2 Multiplier
MIN
x14
x14
MAX
x30
x32
Peripheral Information and Electrical Specifications
198
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