參數(shù)資料
型號(hào): TMS418169P-60
廠商: Texas Instruments, Inc.
英文描述: 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
中文描述: 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等
文件頁(yè)數(shù): 45/67頁(yè)
文件大小: 1464K
代理商: TMS418169P-60
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
MARCH1996
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
PARAMETER MEASUREMENT INFORMATION
RAS
CASx
A0
A8
WE
DSF
TRG
DQ0
DQ15
tc(W)
tw(RL)
tw(RH)
tt
td(RLCH)
td(CLRH)
tw(CL)
td(CHRL)
th(RA)
tt
th(RLCA)
tsu(CA)
tsu(RA)
th(CLCA)
tw(CH)
1
2
3
th(SFR)
tsu(SFR)
tsu(SFC)
th(SFC)
tsu(TRG)
tsu(WMR)
tsu(WCH)
tsu(WRH)
th(RLW)
th(CLW)
tsu(WCL)
th(RWM)
tsu(DQR)
tsu(DCL)
tw(WL)
th(CLD)
th(RLD)
Row
td(CARH)
td(RLCA)
Block Address
th(RDQ)
td(RLCL)
td(CHRL)
th(TRG)
td(CACH)
th(RSF)
For 4-column block write (TMS5516x), block address is A2
A8; for 8-column block write (TMS5517x), block address is A3
A8.
In early-write operations, DQ0
DQ15 are all latched on the first falling edge of CASx. Thus, tsu(DCL) and th(CLD) are referenced only to the first
falling edge of CASx.
Figure 36. Block-Write-Cycle Timing (Early Write)
Table 10. Block-Write-Cycle State Table
CYCLE
STATE
1
2
3
Block-write operation (nonmasked)
H
Don
t care
Column mask
Block-write operation with nonpersistent write-per-bit
L
Write mask
Column mask
Block-write operation with persistent write-per-bit
L
Don
t care
Column mask
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