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參數(shù)資料
| 型號： | TMS418169P-60 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| 中文描述： | 1048576字由16位擴充數(shù)據(jù)輸出高速DRAM等 |
| 文件頁數(shù)： | 25/67頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | TMS418169P-60 |
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
25
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
8-column block write (continued)
A block-write cycle is entered in a manner similar to a DRAM write cycle except DSF is held high on the first
falling edge of CASx. As in a DRAM write operation, CASL and CASU enable the corresponding lower and upper
DRAM DQ bytes to be written, respectively. The column-mask data is input through the DQs and is latched on
either the falling edge of WE or the first falling edge of CASx, whichever occurs later. The 16-bit color-data
register must be loaded prior to performing a block write as described below. Refer to the write-per-bit section
for details on use of the write-mask capability allowing additional performance options.
Example of block write:
block-write column address
=
110000000 (A0
–
A8 from left to right)
bit 0
10111011
11101111
11110000
Lower
Byte
bit 15
color-data register =
write-mask register =
column-mask register =
11000111
11111011
01111010
Upper
Byte
Column-address bits A0
–
A2 are ignored. Block 0 (columns 0
–
7) is selected for both bytes. The lower byte has
DQ0
–
DQ2 and DQ4
–
DQ7 written with bits 0
–
2 and 4
–
7 from the color-data register to columns 0
–
3.
Columns 4
–
7 are not written and retain their previous data due to the column-mask bits 4
–
7 being 0. DQ3 is
not written and retains its previous data due to the write-mask bit 3 being 0.
The upper byte has DQ8
–
DQ12 and DQ14
–
DQ15 written with bits 8
–
12 and 14
–
15 from the color-data
register to columns 1
–
4 and 6. Columns 0, 5, and 7 are not written and retain their previous data due to the
column-mask bits 8, 13, and 15 being 0. DQ13 is not written and retains its previous data due to the
write-mask-register bit 13 being 0. If the previous data was all 0s, the upper byte would contain the data pattern
in Figure 16 after the 8-column block-write operation shown in the example.
DQ14
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ15
Upper Byte
0 1 1 1 1 0 1 0
0 1 1 1 1 0 1 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 1 1 1 1 0 1 0
0 1 1 1 1 0 1 0
0 1 2 3 4 5 6 7
Columns
Figure 16. Example of Upper Byte After 8-Column Block-Write Operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS418169P-70 | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| TMS418169P-80 | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| TMS4500A-15NL | DRAM Controller |
| TMS4500A-20FN | DRAM Controller |
| TMS4500A-20N | DRAM Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS418169P-70 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| TMS418169P-80 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| TMS4256 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS4256-10FM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS4256-10FME | 制造商:TI 制造商全稱:Texas Instruments 功能描述:262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
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