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| 型號： | TMS418169P-60 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS |
| 中文描述： | 1048576字由16位擴充數(shù)據(jù)輸出高速DRAM等 |
| 文件頁數(shù)： | 8/67頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | TMS418169P-60 |
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TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
8
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
Table 2. Function Table
RAS FALL
CASx
FALL
ADDRESS
DQ0
–
DQ15
MNEMONIC
CODE
FUNCTION
CASx
TRG
WE
DSF
DSF
RAS
CASx
§
RAS
CASL
CASU
WE
Reserved (do not use)
L
L
L
L
X
X
X
X
X
—
CBR refresh (no reset) and stop-point set
L
X
L
H
X
Stop
Point
#
X
X
X
CBRS
CBR refresh (option reset)
||
L
X
H
L
X
X
X
X
X
CBR
CBR refresh (no reset)
L
X
H
H
X
X
X
X
X
CBRN
Full-register transfer
H
L
H
L
X
Row
Addr
Tap
Point
X
X
RT
Split-register transfer
H
L
H
H
X
Row
Addr
Tap
Point
X
X
SRT
DRAM write (nonmasked)
H
H
H
L
L
Row
Addr
Col
Addr
X
Valid
Data
RW
DRAM write (nonpersistent write-per-bit)
H
H
L
L
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
RWM
DRAM write (persistent write-per-bit)
H
H
L
L
L
Row
Addr
Col
Addr
X
Valid
Data
RWM
DRAM block write (nonmasked)
H
H
H
L
H
Row
Addr
Block
Addr
X
Col
Mask
BW
DRAM block write (nonpersistent write-per-bit)
H
H
L
L
H
Row
Addr
Block
Addr
Write
Mask
Col
Mask
BWM
DRAM block write (persistent write-per-bit)
H
H
L
L
H
Row
Addr
Block
Addr
X
Col
Mask
BWM
Load write-mask register
H
H
H
H
L
Refresh
Addr
X
X
Write
Mask
LMR
Load color register
H
H
H
H
H
Refresh
Addr
X
X
Color
Data
LCR
Legend:
X
Col Mask
Write Mask
DQ0
–
DQ15 are latched on either the falling edge of WE or the first falling edge of CASx, whichever occurs later.
Logic L is selected when either or both CASL and CASU are low.
§
The column address, the block address, or the tap point is latched on the first falling edge of CASx depending upon which function is executed.
CBRS cycle should be performed immediately after the power-up initialization for stop-point mode.
#A0
–
A3, A8: don
’
t care; A4
–
A7 : stop-point code
||CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
CBR refresh (no reset) mode does not end persistent write-per-bit mode or stop-point mode.
For 4-column block write (TMS5516x), block address is A2
–
A8; for 8-column block write (TMS5517x), block address is A3
–
A8.
Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option reset)
cycle.
=
=
=
Don
’
t care
H: Write to address/column enabled
H: Write to I/O enabled
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