參數(shù)資料
型號: TMS320LC2404APZ
廠商: Texas Instruments, Inc.
英文描述: DUAL LOCK FASTENER 1.5 SQ
中文描述: DSP控制器
文件頁數(shù): 84/133頁
文件大?。?/td> 1672K
代理商: TMS320LC2404APZ
SPRS145J JULY 2000 REVISED NOVEMER 2004
84
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
low-power mode timing
switching characteristics over recommended operating conditions [H = 0.5t
c(CO)
]
(see Figure 30, Figure 31, and Figure 32)
PARAMETER
LOW-POWER MODES
IDLE1
MIN
TYP
MAX
UNIT
td(WAKE-A)
Delay time, CLKOUT switching to
program execution resume
LPM0
12
×
tc(CO)
15
×
tc(CO)
ns
IDLE2
LPM1
td(IDLE-COH)
Delay time, Idle instruction executed to
CLKOUT high
IDLE2
LPM1
4tc(CO)
ns
td(WAKE-OSC)
Delay time, wakeup interrupt
asserted to oscillator running
HALT
{PLL/OSC power down}
LPM2
OSC start-up
time
ms
td(IDLE-OSC)
Delay time, Idle instruction executed to
oscillator power off
4tc(CO)
ns
td(EX)
Delay time, reset vector executed after PLL lock time
36H
ns
WAKE INT
CLKOUT
A0A15
td(WAKEA)
WAKE INT can be any valid interrupt or RESET.
Figure 30. IDLE1 Entry and Exit Timing LPM0
td(WAKEA)
td(IDLECOH)
WAKE INT
CLKOUT
A0A15
WAKE INT can be any valid interrupt or RESET.
Figure 31. IDLE2 Entry and Exit Timing LPM1
td(EX)
td(IDLECOH)
td(IDLEOSC)
RESET
CLKOUT
A0A15
td(WAKEOSC)
tw(RSL)
tp
Figure 32. HALT Mode LPM2
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