參數(shù)資料
型號： TMS320LC2404APZ
廠商： Texas Instruments, Inc.
英文描述： DUAL LOCK FASTENER 1.5 SQ
中文描述： DSP控制器
文件頁數(shù)： 81/133頁
文件大?。?/td> 1672K
代理商： TMS320LC2404APZ
SPRS145J JULY 2000 REVISED NOVEMER 2004
81
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
RS timing
timing requirements for a reset [H = 0.5t
c(CO)
] (see Figure 27 and Figure 28)
MIN
NOM
MAX
UNIT
tw(RSL)
Pulse duration, stable CLKIN to RS high
8tc(CI)
cycles
tw(RSL2)
tp
td(EX)
During power-on reset, the device can continue to hold the RS pin low for another 128 CLKIN cycles.
Pulse duration, RS low
8tc(CI)
cycles
PLL lock-up time
4096tc(CI)
cycles
Delay time, reset vector executed after PLL lock time
36H
ns
XTAL1
(See Note B)
Address/
Data/
Control
NOTES: A. Be certain that the emulation logic is reset before de-asserting the device reset. That is, TRST of the device is not driven high before
the device reset is de-asserted. This is applicable to XDS510
, XDS510PP
, and XDS510PP+
class of emulators. New
generation emulators such as SPI515
and XDS510 USB
emulators have built-in protection mechanism to take care of this
requirement.
B. XTAL1 refers to the internal oscillator clock if on-chip oscillator is used.
C. tOSCST is the oscillator start-up time, which is dependent on crystal/resonator and board design.
D. All I/Os contain a clamp to VDD. Inputs of approximately 0.7 V above VDD will cause the I/O to sink current. I/Os containing pullups
or pulldowns will always sink/source a small amount of current once powered.
CLKOUT
RS
tw(RSL)
tp
td(EX)
VDD/VDDO
CLKIN
BOOT_EN/XF
tOSCST
(See Note C)
BOOT_EN
I/Os
XF
Code-Dependent
Address/Data/ConValid
Hi-Z (See Note D)
Figure 27. Power-on Reset (See Note A)
XDS510PP+, SP515, and XDS510 USB are trademarks of Spectrum Digital.
XDS510 and XDS510PP, are trademarks of Texas Instruments.
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