參數(shù)資料
型號： TMS320LC2404APZ
廠商： Texas Instruments, Inc.
英文描述： DUAL LOCK FASTENER 1.5 SQ
中文描述： DSP控制器
文件頁數(shù)： 108/133頁
文件大?。?/td> 1672K
代理商： TMS320LC2404APZ
SPRS145J JULY 2000 REVISED NOVEMBER 2004
108
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
10-bit analog-to-digital converter (ADC) (continued)
operating characteristics over recommended operating condition ranges
PARAMETER
DESCRIPTION
MIN
TYP
10
MAX
15
UNIT
mA
VCCA = 3.3 V
ICCA
Analog supply current
VCCA = VREFHI = 3.3 V
PLL or OSC power
down
1
μ
A
IADREFHI
VREFHI input current
0.75
1.5
mA
IADCIN
Analog input leakage
1
μ
A
Cai
Analog input capacitance
Typical capacitive load on
analog input pin
Non-sampling
10
pF
Sampling
30
td(PU)
Delay time, power-up to ADC valid
Time to stabilize analog stage after power-up
10
μ
s
ZAI
Analog input source impedance
Analog input source impedance needed for
conversions to remain within specifications at min
tw(SH)
53
10
Zero-offset error
2
LSB
Absolute resolution = 3.22 mV. At VREFHI = 3.3 V and VREFLO = 0 V, this is one LSB. As VREFHI decreases, VREFLO increases, or both, the LSB
size decreases. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
E
DNL
and E
INL
PARAMETER
DESCRIPTION
CLKOUT
MIN
MAX
UNIT
EDNL
Differential nonlinearity error
Difference between the actual step width
and the ideal value
30 MHz
2
LSB
EINL
Integral nonlinearity error
Maximum deviation from the best straight
line through the ADC transfer
characteristics, excluding the quantization
error
30 MHz
2
LSB
Test conditions: VREFHI = VCCA, VREFLO = VSSA
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相關代理商/技術參數(shù)
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