參數(shù)資料
型號： TMS320LC2404APZ
廠商： Texas Instruments, Inc.
英文描述： DUAL LOCK FASTENER 1.5 SQ
中文描述： DSP控制器
文件頁數(shù)： 60/133頁
文件大小： 1672K
代理商： TMS320LC2404APZ
SPRS145J JULY 2000 REVISED NOVEMBER 2004
60
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
clock domains
All 240xA-based devices have two clock domains:
1.
CPU clock domain consists of the clock for most of the CPU logic
2.
System clock domain consists of the peripheral clock (which is derived from CLKOUT of the CPU) and
the clock for the interrupt logic in the CPU.
When the CPU goes into IDLE mode, the CPU clock domain is stopped while the system clock domain continues
to run. This mode is also known as IDLE1 mode. The 240xA CPU also contains support for a second IDLE mode,
IDLE2. By asserting IDLE2 to the 240xA CPU, both the CPU clock domain and the system clock domain are
stopped, allowing further power savings. A third low-power mode, HALT mode, the deepest, is possible if the
oscillator and WDCLK are also shut down when in IDLE2 mode.
Two control bits, LPM1 and LPM0, specify which of the three possible low-power modes is entered when the
IDLE instruction is executed (see Table 11). These bits are located in the System Control and Status
Register 1 (SCSR1), and they are described in the
TMS320LF/LC240xA DSP Controllers Reference Guide:
System and Peripherals
(literature number SPRU357).
Table 11. Low-Power Modes Summary
LOW-POWER MODE
LPMx BITS
SCSR1
[13:12]
CPU
CLOCK
DOMAIN
SYSTEM
CLOCK
DOMAIN
WDCLK
STATUS
PLL
STATUS
OSC
STATUS
FLASH
POWER
EXIT
CONDITION
CPU running normally
XX
On
On
On
On
On
On
—
IDLE1 (LPM0)
00
Off
On
On
On
On
On
Peripheral
Interrupt,
External Interrupt,
Reset,
PDPINTA/B
IDLE2 (LPM1)
01
Off
Off
On
On
On
On
Wakeup
Interrupts,
External Interrupt,
Reset,
PDPINTA/B
HALT (LPM2)
[PLL/OSC power down]
1X
Off
Off
Off
Off
Off
Off
Reset,
PDPINTA/B
The Flash must be powered down by the user code prior to entering LPM2. For more details, see the
TMS320LF/LC240xA DSP Controllers
Reference Guide: System and Peripherals
(literature number SPRU357).
other power-down options
240xA devices have clock-enable bits to the following on-chip peripherals: ADC, SCI, SPI, CAN, EVB, and EVA.
Clock to these peripherals are disabled after reset; thus, start-up power can be low for the device.
Depending on the application, these peripherals can be turned on/off to achieve low power.
See the SCSR1 register for details on the peripheral clock enable bits.
digital I/O and shared pin functions
The 240xA has up to 41 general-purpose, bidirectional, digital I/O (GPIO) pins—most of which are shared
between primary functions and I/O. Most I/O pins of the 240xA are shared with other functions. The digital I/O
ports module provides a flexible method for controlling both dedicated I/O and shared pin functions. All I/O and
shared pin functions are controlled using eight 16-bit registers. These registers are divided into two types:
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