參數(shù)資料
型號： TMS320LC2404APZ
廠商： Texas Instruments, Inc.
英文描述： DUAL LOCK FASTENER 1.5 SQ
中文描述： DSP控制器
文件頁數(shù)： 107/133頁
文件大?。?/td> 1672K
代理商： TMS320LC2404APZ
SPRS145J JULY 2000 REVISED NOVEMBER 2004
107
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
10-bit analog-to-digital converter (ADC)
The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as V
CCA
and V
SSA
.
The power bus isolation is to enhance ADC performance by preventing digital switching noise of the logic
circuitry that can be present on V
SS
and V
CC
from coupling into the ADC analog stage. All ADC specifications
are given with respect to V
SSA
unless otherwise noted.
Resolution
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monotonic
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output conversion mode
000h to 3FFh (000h for V
I
≤
V
REFLO
; 3FFh for V
I
≥
V
REFHI
)
. . . . . . . . . . . . . . . . . . .
Minimum conversion time (including sample time)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10-bit (1024 values)
Assured
500 ns
recommended operating conditions
MIN
NOM
MAX
UNIT
VCCA
VSSA
VREFHI
VREFLO
VAI
VREFHI and VREFLO must be stable, within
±
1/2 LSB of the required resolution, during the entire conversion time.
VREFHI can be from 2.0 V to VCCA; however, the accuracy of the ADC depends on the ground bounce and noise on the target board.
Analog supply voltage
3.0
3.3
3.6
V
Analog ground
Analog supply reference source
Analog ground reference source
0
V
VCCA
V
VSSA
V
Analog input voltage, ADCIN00ADCIN07
VREFLO
VREFHI
V
ADC operating frequency
MIN
MAX
UNIT
ADC operating frequency
4
30
MHz
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