參數(shù)資料
型號: TMS320LC2404APZ
廠商: Texas Instruments, Inc.
英文描述: DUAL LOCK FASTENER 1.5 SQ
中文描述: DSP控制器
文件頁數(shù): 79/133頁
文件大?。?/td> 1672K
代理商: TMS320LC2404APZ
SPRS145J JULY 2000 REVISED NOVEMER 2004
79
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
A
A[15:0]
MS
Memory strobe pins IS, DS, or PS
Cl
XTAL1/CLKIN
R
READY
CO
CLKOUT
RD
Read cycle or RD
D
D[15:0]
RS
RESET pin RS
INT
XINT1, XINT2
W
Write cycle or WE
Lowercase subscripts and their meanings:
Letters and symbols and their meanings:
a
access time
H
High
c
cycle time (period)
L
Low
d
delay time
V
Valid
f
fall time
X
Unknown, changing, or don’t care level
h
hold time
Z
High impedance
r
rise time
su
setup time
t
transition time
v
valid time
w
pulse duration (width)
general notes on timing
All output signals from the 240xA devices (including CLKOUT) are derived from an internal clock such that all
output transitions for a given half-cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, see the appropriate cycle description section of this data sheet.
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