參數(shù)資料
型號: TMS320C241PGS
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 13/116頁
文件大?。?/td> 1485K
代理商: TMS320C241PGS
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions - ’F243 PGE Package (Continued)
NAME
144
QFP
NO.
TYPE
RESET
STATE
DESCRIPTION
NO CONNECTS
DNC
12
Do not connect Reserved for test
Do not connect. Reserved for test.
97
1
2
5
7
9
11
NC
13
No internal connection made to this pin
132
133
134
136
138
140
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.
Data is in output mode when AVIS is enabled. At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS
is enabled.
NOTE:
Bold, italicized pin names
indicate pin function after reset.
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