參數(shù)資料
型號(hào): TMS320C241PGS
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 12/116頁(yè)
文件大?。?/td> 1485K
代理商: TMS320C241PGS
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
TMS320F243, TMS320F241
DSP CONTROLLERS
SPRS064B – DECEMBER 1997 – REVISED FEBRUARY 1999
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Terminal Functions - ’F243 PGE Package (Continued)
NAME
144
QFP
NO.
TYPE
RESET
STATE
DESCRIPTION
TEST SIGNALS (CONTINUED)
TRST
30
I
I
JTAG test reset with internal pulldown. TRST, when driven high, gives
the scan system control of the operations of the device. If this signal is
not connected or driven low, the device operates in its functional mode,
and the test reset signals are ignored.
EMU0
45
I/O
I
Emulator I/O pin 0 with internal pullup. When TRST is driven high, this
pin is used as an interrupt to or from the emulator system and is defined
as input/output through the JTAG scan.
EMU1/OFF
47
I/O
I
Emulator I/O pin 1 with internal pullup. When TRST is driven high, this
pin is used as an interrupt to or from the emulator system and is defined
as input/output through JTAG scan.
SUPPLY SIGNALS
14
15
36
37
40
70
VSSO
73
Digital logic and buffer ground reference
108
111
117
124
129
131
34
39
VDDO
72
Digital logic and buffer supply voltage
75
106
109
17
VDD
53
Digital logic supply voltage
125
16
VSS
32
Digital logic ground reference
51
127
I = input, O = output, Z = high impedance
The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is
an output, its level at reset is indicated.
§ In silicon revisions 2.0-TMX and 2.1-TMS, this pin is level-sensitive and can cause multiple interrupts when held low.
Data is in output mode when AVIS is enabled. At reset, the device comes up with AVIS mode enabled. The data bus is in output mode while AVIS
is enabled.
NOTE:
Bold, italicized pin names
indicate pin function after reset.
相關(guān)PDF資料
PDF描述
TMS320F241FNQ 16-Bit Digital Signal Processor
TMS320F241PGQ 16-Bit Digital Signal Processor
TMS320F243PGEQ 16-Bit Digital Signal Processor
TMS320F243PGES 16-Bit Digital Signal Processor
TMS320C3X 32-Bit Digital Signal Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMS320C242 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DSP CONTROLLER
TMS320C242FN 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DSP CONTROLLER
TMS320C242FNA 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:16-Bit Digital Signal Processor
TMS320C242FNS 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:16-Bit Digital Signal Processor
TMS320C242PG 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:DSP CONTROLLER